1/* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25#ifndef _MEM_H_ 26#define _MEM_H_ 27 28#define CS0 0x0 29#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31#ifndef __ASSEMBLY__ 32enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37}; 38#endif /* __ASSEMBLY__ */ 39 40#define EARLY_INIT 1 41 42/* Slower full frequency range default timings for x32 operation*/ 43#define SDRC_SHARING 0x00000100 44#define SDRC_MR_0_SDR 0x00000031 45 46#define DLL_OFFSET 0 47#define DLL_WRITEDDRCLKX2DIS 1 48#define DLL_ENADLL 1 49#define DLL_LOCKDLL 0 50#define DLL_DLLPHASE_72 0 51#define DLL_DLLPHASE_90 1 52 53/* rkw - need to find of 90/72 degree recommendation for speed like before */ 54#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56 57/* Infineon part of 3430SDP (165MHz optimized) 6.06ns 58 * ACTIMA 59 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 60 * TDPL (Twr) = 15/6 = 2.5 -> 3 61 * TRRD = 12/6 = 2 62 * TRCD = 18/6 = 3 63 * TRP = 18/6 = 3 64 * TRAS = 42/6 = 7 65 * TRC = 60/6 = 10 66 * TRFC = 72/6 = 12 67 * ACTIMB 68 * TCKE = 2 69 * XSR = 120/6 = 20 70 */ 71#define INFINEON_TDAL_165 6 72#define INFINEON_TDPL_165 3 73#define INFINEON_TRRD_165 2 74#define INFINEON_TRCD_165 3 75#define INFINEON_TRP_165 3 76#define INFINEON_TRAS_165 7 77#define INFINEON_TRC_165 10 78#define INFINEON_TRFC_165 12 79#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ 80 (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ 81 (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ 82 (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ 83 (INFINEON_TDAL_165)) 84 85#define INFINEON_TWTR_165 1 86#define INFINEON_TCKE_165 2 87#define INFINEON_TXP_165 2 88#define INFINEON_XSR_165 20 89#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ 90 (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ 91 (INFINEON_TWTR_165 << 16)) 92 93/* Micron part of 3430 EVM (165MHz optimized) 6.06ns 94 * ACTIMA 95 * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 96 * TDPL (Twr) = 15/6 = 2.5 -> 3 97 * TRRD = 12/6 = 2 98 * TRCD = 18/6 = 3 99 * TRP = 18/6 = 3 100 * TRAS = 42/6 = 7 101 * TRC = 60/6 = 10 102 * TRFC = 125/6 = 21 103 * ACTIMB 104 * TWTR = 1 105 * TCKE = 1 106 * TXSR = 138/6 = 23 107 * TXP = 25/6 = 4.1 ~5 108 */ 109#define MICRON_TDAL_165 6 110#define MICRON_TDPL_165 3 111#define MICRON_TRRD_165 2 112#define MICRON_TRCD_165 3 113#define MICRON_TRP_165 3 114#define MICRON_TRAS_165 7 115#define MICRON_TRC_165 10 116#define MICRON_TRFC_165 21 117#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ 118 (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ 119 (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ 120 (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ 121 (MICRON_TDAL_165)) 122 123#define MICRON_TWTR_165 1 124#define MICRON_TCKE_165 1 125#define MICRON_XSR_165 23 126#define MICRON_TXP_165 5 127#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ 128 (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ 129 (MICRON_TWTR_165 << 16)) 130 131/* 132 * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns 133 * ACTIMA 134 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 135 * TDPL (Twr) = 15/6 = 2.5 -> 3 136 * TRRD = 12/6 = 2 137 * TRCD = 22.5/6 = 3.75 -> 4 138 * TRP = 18/6 = 3 139 * TRAS = 42/6 = 7 140 * TRC = 60/6 = 10 141 * TRFC = 140/6 = 23.3 -> 24 142 * ACTIMB 143 * TWTR = 2 144 * TCKE = 2 145 * TXSR = 200/6 = 33.3 -> 34 146 * TXP = 1.0 + 1.1 = 2.1 -> 3 147 */ 148#define NUMONYX_TDAL_165 6 149#define NUMONYX_TDPL_165 3 150#define NUMONYX_TRRD_165 2 151#define NUMONYX_TRCD_165 4 152#define NUMONYX_TRP_165 3 153#define NUMONYX_TRAS_165 7 154#define NUMONYX_TRC_165 10 155#define NUMONYX_TRFC_165 24 156#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \ 157 (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \ 158 (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \ 159 (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \ 160 (NUMONYX_TDAL_165)) 161 162#define NUMONYX_TWTR_165 2 163#define NUMONYX_TCKE_165 2 164#define NUMONYX_TXP_165 3 165#define NUMONYX_XSR_165 34 166#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \ 167 (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ 168 (NUMONYX_TWTR_165 << 16)) 169 170#ifdef CONFIG_OMAP3_INFINEON_DDR 171#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 172#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 173#endif 174#ifdef CONFIG_OMAP3_MICRON_DDR 175#define V_ACTIMA_165 MICRON_V_ACTIMA_165 176#define V_ACTIMB_165 MICRON_V_ACTIMB_165 177#endif 178#ifdef CONFIG_OMAP3_NUMONYX_DDR 179#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 180#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 181#endif 182 183#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 184#error "Please choose the right DDR type in config header" 185#endif 186 187/* 188 * GPMC settings - 189 * Definitions is as per the following format 190 * #define <PART>_GPMC_CONFIG<x> <value> 191 * Where: 192 * PART is the part name e.g. STNOR - Intel Strata Flash 193 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 194 * Value is corresponding value 195 * 196 * For every valid PRCM configuration there should be only one definition of 197 * the same. if values are independent of the board, this definition will be 198 * present in this file if values are dependent on the board, then this should 199 * go into corresponding mem-boardName.h file 200 * 201 * Currently valid part Names are (PART): 202 * STNOR - Intel Strata Flash 203 * SMNAND - Samsung NAND 204 * MPDB - H4 MPDB board 205 * SBNOR - Sibley NOR 206 * MNAND - Micron Large page x16 NAND 207 * ONNAND - Samsung One NAND 208 * 209 * include/configs/file.h contains the defn - for all CS we are interested 210 * #define OMAP34XX_GPMC_CSx PART 211 * #define OMAP34XX_GPMC_CSx_SIZE Size 212 * #define OMAP34XX_GPMC_CSx_MAP Map 213 * Where: 214 * x - CS number 215 * PART - Part Name as defined above 216 * SIZE - how big is the mapping to be 217 * GPMC_SIZE_128M - 0x8 218 * GPMC_SIZE_64M - 0xC 219 * GPMC_SIZE_32M - 0xE 220 * GPMC_SIZE_16M - 0xF 221 * MAP - Map this CS to which address(GPMC address space)- Absolute address 222 * >>24 before being used. 223 */ 224#define GPMC_SIZE_128M 0x8 225#define GPMC_SIZE_64M 0xC 226#define GPMC_SIZE_32M 0xE 227#define GPMC_SIZE_16M 0xF 228 229#define SMNAND_GPMC_CONFIG1 0x00000800 230#define SMNAND_GPMC_CONFIG2 0x00141400 231#define SMNAND_GPMC_CONFIG3 0x00141400 232#define SMNAND_GPMC_CONFIG4 0x0F010F01 233#define SMNAND_GPMC_CONFIG5 0x010C1414 234#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 235#define SMNAND_GPMC_CONFIG7 0x00000C44 236 237#define M_NAND_GPMC_CONFIG1 0x00001800 238#define M_NAND_GPMC_CONFIG2 0x00141400 239#define M_NAND_GPMC_CONFIG3 0x00141400 240#define M_NAND_GPMC_CONFIG4 0x0F010F01 241#define M_NAND_GPMC_CONFIG5 0x010C1414 242#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 243#define M_NAND_GPMC_CONFIG7 0x00000C44 244 245#define STNOR_GPMC_CONFIG1 0x3 246#define STNOR_GPMC_CONFIG2 0x00151501 247#define STNOR_GPMC_CONFIG3 0x00060602 248#define STNOR_GPMC_CONFIG4 0x11091109 249#define STNOR_GPMC_CONFIG5 0x01141F1F 250#define STNOR_GPMC_CONFIG6 0x000004c4 251 252#define SIBNOR_GPMC_CONFIG1 0x1200 253#define SIBNOR_GPMC_CONFIG2 0x001f1f00 254#define SIBNOR_GPMC_CONFIG3 0x00080802 255#define SIBNOR_GPMC_CONFIG4 0x1C091C09 256#define SIBNOR_GPMC_CONFIG5 0x01131F1F 257#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 258 259#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 260#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 261#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 262#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 263#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 264#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 265 266#define MPDB_GPMC_CONFIG1 0x00011000 267#define MPDB_GPMC_CONFIG2 0x001f1f01 268#define MPDB_GPMC_CONFIG3 0x00080803 269#define MPDB_GPMC_CONFIG4 0x1c0b1c0a 270#define MPDB_GPMC_CONFIG5 0x041f1F1F 271#define MPDB_GPMC_CONFIG6 0x1F0F04C4 272 273#define P2_GPMC_CONFIG1 0x0 274#define P2_GPMC_CONFIG2 0x0 275#define P2_GPMC_CONFIG3 0x0 276#define P2_GPMC_CONFIG4 0x0 277#define P2_GPMC_CONFIG5 0x0 278#define P2_GPMC_CONFIG6 0x0 279 280#define ONENAND_GPMC_CONFIG1 0x00001200 281#define ONENAND_GPMC_CONFIG2 0x000F0F01 282#define ONENAND_GPMC_CONFIG3 0x00030301 283#define ONENAND_GPMC_CONFIG4 0x0F040F04 284#define ONENAND_GPMC_CONFIG5 0x010F1010 285#define ONENAND_GPMC_CONFIG6 0x1F060000 286 287#define NET_GPMC_CONFIG1 0x00001000 288#define NET_GPMC_CONFIG2 0x001e1e01 289#define NET_GPMC_CONFIG3 0x00080300 290#define NET_GPMC_CONFIG4 0x1c091c09 291#define NET_GPMC_CONFIG5 0x04181f1f 292#define NET_GPMC_CONFIG6 0x00000FCF 293#define NET_GPMC_CONFIG7 0x00000f6c 294 295/* max number of GPMC Chip Selects */ 296#define GPMC_MAX_CS 8 297/* max number of GPMC regs */ 298#define GPMC_MAX_REG 7 299 300#define PISMO1_NOR 1 301#define PISMO1_NAND 2 302#define PISMO2_CS0 3 303#define PISMO2_CS1 4 304#define PISMO1_ONENAND 5 305#define DBG_MPDB 6 306#define PISMO2_NAND_CS0 7 307#define PISMO2_NAND_CS1 8 308 309/* make it readable for the gpmc_init */ 310#define PISMO1_NOR_BASE FLASH_BASE 311#define PISMO1_NAND_BASE NAND_BASE 312#define PISMO2_CS0_BASE PISMO2_MAP1 313#define PISMO1_ONEN_BASE ONENAND_MAP 314#define DBG_MPDB_BASE DEBUG_BASE 315 316#ifndef __ASSEMBLY__ 317 318/* Function prototypes */ 319void mem_init(void); 320 321u32 is_mem_sdr(void); 322u32 mem_ok(u32 cs); 323 324u32 get_sdr_cs_size(u32); 325u32 get_sdr_cs_offset(u32); 326 327#endif /* __ASSEMBLY__ */ 328 329#endif /* endif _MEM_H_ */ 330