1/* 2 * U-boot - start.S Startup file for Blackfin u-boot 3 * 4 * Copyright (c) 2005-2008 Analog Devices Inc. 5 * 6 * This file is based on head.S 7 * Copyright (c) 2003 Metrowerks/Motorola 8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, 9 * Kenneth Albanowski <kjahds@kjahds.com>, 10 * The Silver Hammer Group, Ltd. 11 * (c) 1995, Dionne & Associates 12 * (c) 1995, DKG Display Tech. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 30 * MA 02110-1301 USA 31 */ 32 33#include <config.h> 34#include <asm/blackfin.h> 35#include <asm/mach-common/bits/core.h> 36#include <asm/mach-common/bits/pll.h> 37 38#include "serial.h" 39 40/* It may seem odd that we make calls to functions even though we haven't 41 * relocated ourselves yet out of {flash,ram,wherever}. This is OK because 42 * the "call" instruction in the Blackfin architecture is actually PC 43 * relative. So we can call functions all we want and not worry about them 44 * not being relocated yet. 45 */ 46 47.text 48ENTRY(_start) 49 50 /* Set our initial stack to L1 scratch space */ 51 sp.l = LO(L1_SRAM_SCRATCH_END - 20); 52 sp.h = HI(L1_SRAM_SCRATCH_END - 20); 53 54 /* Optimization register tricks: keep a base value in the 55 * reserved P registers so we use the load/store with an 56 * offset syntax. R0 = [P5 + <constant>]; 57 * P4 - system MMR base 58 * P5 - core MMR base 59 */ 60#ifdef CONFIG_HW_WATCHDOG 61 p4.l = 0; 62 p4.h = HI(SYSMMR_BASE); 63#endif 64 p5.l = 0; 65 p5.h = HI(COREMMR_BASE); 66 67#ifdef CONFIG_HW_WATCHDOG 68# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START 69# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000 70# endif 71 /* Program the watchdog with an initial timeout of ~5 seconds. 72 * That should be long enough to bootstrap ourselves up and 73 * then the common u-boot code can take over. 74 */ 75 r0 = 0; 76 r0.h = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START)); 77 [p4 + (WDOG_CNT - SYSMMR_BASE)] = r0; 78 /* fire up the watchdog - R0.L above needs to be 0x0000 */ 79 W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0; 80#endif 81 82 /* Turn on the serial for debugging the init process */ 83 serial_early_init 84 serial_early_set_baud 85 86 serial_early_puts("Init Registers"); 87 88 /* Disable self-nested interrupts and enable CYCLES for udelay() */ 89 R0 = CCEN | 0x30; 90 SYSCFG = R0; 91 92 /* Zero out registers required by Blackfin ABI. 93 * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface 94 */ 95 r1 = 0 (x); 96 /* Disable circular buffers */ 97 l0 = r1; 98 l1 = r1; 99 l2 = r1; 100 l3 = r1; 101 /* Disable hardware loops in case we were started by 'go' */ 102 lc0 = r1; 103 lc1 = r1; 104 105 /* Save RETX so we can pass it while booting Linux */ 106 r7 = RETX; 107 108#if CONFIG_MEM_SIZE 109 /* Figure out where we are currently executing so that we can decide 110 * how to best reprogram and relocate things. We'll pass below: 111 * R4: load address of _start 112 * R5: current (not load) address of _start 113 */ 114 serial_early_puts("Find ourselves"); 115 116 call _get_pc; 117.Loffset: 118 r1.l = .Loffset; 119 r1.h = .Loffset; 120 r4.l = _start; 121 r4.h = _start; 122 r3 = r1 - r4; 123 r5 = r0 - r3; 124 125 /* Inform upper layers if we had to do the relocation ourselves. 126 * This allows us to detect whether we were loaded by 'go 0x1000' 127 * or by the bootrom from an LDR. "R6" is "loaded_from_ldr". 128 */ 129 r6 = 1 (x); 130 cc = r4 == r5; 131 if cc jump .Lnorelocate; 132 r6 = 0 (x); 133 134 /* Turn off caches as they require CPLBs and a CPLB miss requires 135 * a software exception handler to process it. But we're about to 136 * clobber any previous executing software (like U-Boot that just 137 * launched a new U-Boot via 'go'), so any handler state will be 138 * unreliable after the memcpy below. 139 */ 140 serial_early_puts("Kill Caches"); 141 r0 = 0; 142 [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r0; 143 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r0; 144 ssync; 145 146 /* In bypass mode, we don't have an LDR with an init block 147 * so we need to explicitly call it ourselves. This will 148 * reprogram our clocks, memory, and setup our async banks. 149 */ 150 serial_early_puts("Program Clocks"); 151 152 /* if we're executing >=0x20000000, then we dont need to dma */ 153 r3 = 0x0; 154 r3.h = 0x2000; 155 cc = r5 < r3 (iu); 156 if cc jump .Ldma_and_reprogram; 157#else 158 r6 = 1 (x); /* fake loaded_from_ldr = 1 */ 159#endif 160 r0 = 0 (x); /* set bootstruct to NULL */ 161 call _initcode; 162 jump .Lprogrammed; 163 164 /* we're sitting in external memory, so dma into L1 and reprogram */ 165.Ldma_and_reprogram: 166 r0.l = LO(L1_INST_SRAM); 167 r0.h = HI(L1_INST_SRAM); 168 r1.l = __initcode_lma; 169 r1.h = __initcode_lma; 170 r2.l = __initcode_len; 171 r2.h = __initcode_len; 172 r1 = r1 - r4; /* convert r1 from load address of initcode ... */ 173 r1 = r1 + r5; /* ... to current (not load) address of initcode */ 174 p3 = r0; 175 call _dma_memcpy_nocache; 176 r0 = 0 (x); /* set bootstruct to NULL */ 177 call (p3); 178 179 /* Since we reprogrammed SCLK, we need to update the serial divisor */ 180.Lprogrammed: 181 serial_early_set_baud 182 183#if CONFIG_MEM_SIZE 184 /* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded 185 * monitor location in the end of RAM. We know that memcpy() only 186 * uses registers, so it is safe to call here. Note that this only 187 * copies to external memory ... we do not start executing out of 188 * it yet (see "lower to 15" below). 189 */ 190 serial_early_puts("Relocate"); 191 r0 = r4; 192 r1 = r5; 193 r2.l = LO(CONFIG_SYS_MONITOR_LEN); 194 r2.h = HI(CONFIG_SYS_MONITOR_LEN); 195 call _memcpy_ASM; 196#endif 197 198 /* Initialize BSS section ... we know that memset() does not 199 * use the BSS, so it is safe to call here. The bootrom LDR 200 * takes care of clearing things for us. 201 */ 202 serial_early_puts("Zero BSS"); 203 r0.l = __bss_vma; 204 r0.h = __bss_vma; 205 r1 = 0 (x); 206 r2.l = __bss_len; 207 r2.h = __bss_len; 208 call _memset; 209 210.Lnorelocate: 211 212 /* Setup the actual stack in external memory */ 213 sp.h = HI(CONFIG_STACKBASE); 214 sp.l = LO(CONFIG_STACKBASE); 215 fp = sp; 216 217 /* Now lower ourselves from the highest interrupt level to 218 * the lowest. We do this by masking all interrupts but 15, 219 * setting the 15 handler to ".Lenable_nested", raising the 15 220 * interrupt, and then returning from the highest interrupt 221 * level to the dummy "jump" until the interrupt controller 222 * services the pending 15 interrupt. If executing out of 223 * flash, these steps also changes the code flow from flash 224 * to external memory. 225 */ 226 serial_early_puts("Lower to 15"); 227 r0 = r7; 228 r1 = r6; 229 p1.l = .Lenable_nested; 230 p1.h = .Lenable_nested; 231 [p5 + (EVT15 - COREMMR_BASE)] = p1; 232 r7 = EVT_IVG15 (z); 233 sti r7; 234 raise 15; 235 p3.l = .LWAIT_HERE; 236 p3.h = .LWAIT_HERE; 237 reti = p3; 238 rti; 239 240 /* Enable nested interrupts before continuing with cpu init */ 241.Lenable_nested: 242 cli r7; 243 [--sp] = reti; 244 jump.l _cpu_init_f; 245 246.LWAIT_HERE: 247 jump .LWAIT_HERE; 248ENDPROC(_start) 249 250LENTRY(_get_pc) 251 r0 = rets; 252#if ANOMALY_05000371 253 NOP; 254 NOP; 255 NOP; 256#endif 257 rts; 258ENDPROC(_get_pc) 259