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28#include <common.h>
29#include <config.h>
30#include <asm/blackfin.h>
31#include <asm/io.h>
32#include <asm/mach-common/bits/dma.h>
33
34char *strcpy(char *dest, const char *src)
35{
36 char *xdest = dest;
37 char temp = 0;
38
39 __asm__ __volatile__ (
40 "1:\t%2 = B [%1++] (Z);\n\t"
41 "B [%0++] = %2;\n\t"
42 "CC = %2;\n\t"
43 "if cc jump 1b (bp);\n"
44 : "=a"(dest), "=a"(src), "=d"(temp)
45 : "0"(dest), "1"(src), "2"(temp)
46 : "memory");
47
48 return xdest;
49}
50
51char *strncpy(char *dest, const char *src, size_t n)
52{
53 char *xdest = dest;
54 char temp = 0;
55
56 if (n == 0)
57 return xdest;
58
59 __asm__ __volatile__ (
60 "1:\t%3 = B [%1++] (Z);\n\t"
61 "B [%0++] = %3;\n\t"
62 "CC = %3;\n\t"
63 "if ! cc jump 2f;\n\t"
64 "%2 += -1;\n\t"
65 "CC = %2 == 0;\n\t"
66 "if ! cc jump 1b (bp);\n"
67 "2:\n"
68 : "=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
69 : "0"(dest), "1"(src), "2"(n), "3"(temp)
70 : "memory");
71
72 return xdest;
73}
74
75int strcmp(const char *cs, const char *ct)
76{
77 char __res1, __res2;
78
79 __asm__ (
80 "1:\t%2 = B[%0++] (Z);\n\t"
81 "%3 = B[%1++] (Z);\n\t"
82 "CC = %2 == %3;\n\t"
83 "if ! cc jump 2f;\n\t"
84 "CC = %2;\n\t"
85 "if cc jump 1b (bp);\n\t"
86 "jump.s 3f;\n"
87 "2:\t%2 = %2 - %3;\n"
88 "3:\n"
89 : "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
90 : "0"(cs), "1"(ct));
91
92 return __res1;
93}
94
95int strncmp(const char *cs, const char *ct, size_t count)
96{
97 char __res1, __res2;
98
99 if (!count)
100 return 0;
101
102 __asm__(
103 "1:\t%3 = B[%0++] (Z);\n\t"
104 "%4 = B[%1++] (Z);\n\t"
105 "CC = %3 == %4;\n\t"
106 "if ! cc jump 3f;\n\t"
107 "CC = %3;\n\t"
108 "if ! cc jump 4f;\n\t"
109 "%2 += -1;\n\t"
110 "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"
111 "2:\t%3 = 0;\n\t"
112 "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n"
113 "4:"
114 : "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), "=d"(__res2)
115 : "0"(cs), "1"(ct), "2"(count));
116
117 return __res1;
118}
119
120#ifdef bfin_write_MDMA1_D0_IRQ_STATUS
121# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
122# define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA1_D0_START_ADDR
123# define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA1_D0_X_COUNT
124# define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA1_D0_X_MODIFY
125# define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA1_D0_CONFIG
126# define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA1_S0_START_ADDR
127# define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA1_S0_X_COUNT
128# define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA1_S0_X_MODIFY
129# define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA1_S0_CONFIG
130# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
131# define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA1_D0_IRQ_STATUS
132#endif
133
134
135
136
137void dma_memcpy_nocache(void *dst, const void *src, size_t count)
138{
139 uint16_t wdsize, mod;
140
141
142
143
144
145 bfin_write_MDMA_D0_CONFIG(0);
146 bfin_write_MDMA_S0_CONFIG(0);
147 bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
148
149
150 if (((unsigned long)src >= L1_SRAM_SCRATCH &&
151 (unsigned long)src < L1_SRAM_SCRATCH_END) ||
152 ((unsigned long)dst >= L1_SRAM_SCRATCH &&
153 (unsigned long)dst < L1_SRAM_SCRATCH_END))
154 hang();
155
156 if (((unsigned long)dst | (unsigned long)src | count) & 0x1) {
157 wdsize = WDSIZE_8;
158 mod = 1;
159 } else if (((unsigned long)dst | (unsigned long)src | count) & 0x2) {
160 wdsize = WDSIZE_16;
161 count >>= 1;
162 mod = 2;
163 } else {
164 wdsize = WDSIZE_32;
165 count >>= 2;
166 mod = 4;
167 }
168
169
170
171 bfin_write_MDMA_D0_START_ADDR(dst);
172
173 bfin_write_MDMA_D0_X_COUNT(count);
174
175 bfin_write_MDMA_D0_X_MODIFY(mod);
176
177
178 bfin_write_MDMA_S0_START_ADDR(src);
179
180 bfin_write_MDMA_S0_X_COUNT(count);
181
182 bfin_write_MDMA_S0_X_MODIFY(mod);
183
184
185 bfin_write_MDMA_S0_CONFIG(wdsize | DMAEN);
186 bfin_write_MDMA_D0_CONFIG(wdsize | DMAEN | WNR | DI_EN);
187 SSYNC();
188
189 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
190 continue;
191
192 bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
193 bfin_write_MDMA_D0_CONFIG(0);
194 bfin_write_MDMA_S0_CONFIG(0);
195}
196
197
198
199
200void *dma_memcpy(void *dst, const void *src, size_t count)
201{
202 if (dcache_status()) {
203 blackfin_dcache_flush_range(src, src + count);
204 blackfin_dcache_flush_invalidate_range(dst, dst + count);
205 }
206
207 dma_memcpy_nocache(dst, src, count);
208
209 if (icache_status())
210 blackfin_icache_flush_range(dst, dst + count);
211
212 return dst;
213}
214
215
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225
226
227extern void *memcpy_ASM(void *dst, const void *src, size_t count);
228void *memcpy(void *dst, const void *src, size_t count)
229{
230 if (!count)
231 return dst;
232
233#ifdef CONFIG_CMD_KGDB
234 if (src >= (void *)SYSMMR_BASE) {
235 if (count == 2 && (unsigned long)src % 2 == 0) {
236 u16 mmr = bfin_read16(src);
237 memcpy(dst, &mmr, sizeof(mmr));
238 return dst;
239 }
240 if (count == 4 && (unsigned long)src % 4 == 0) {
241 u32 mmr = bfin_read32(src);
242 memcpy(dst, &mmr, sizeof(mmr));
243 return dst;
244 }
245
246 memset(dst, 0xad, count);
247 return dst;
248 }
249 if (dst >= (void *)SYSMMR_BASE) {
250 if (count == 2 && (unsigned long)dst % 2 == 0) {
251 u16 mmr;
252 memcpy(&mmr, src, sizeof(mmr));
253 bfin_write16(dst, mmr);
254 return dst;
255 }
256 if (count == 4 && (unsigned long)dst % 4 == 0) {
257 u32 mmr;
258 memcpy(&mmr, src, sizeof(mmr));
259 bfin_write32(dst, mmr);
260 return dst;
261 }
262
263 memset(dst, 0xad, count);
264 return dst;
265 }
266#endif
267
268
269 if (addr_bfin_on_chip_mem(dst) || addr_bfin_on_chip_mem(src))
270 return dma_memcpy(dst, src, count);
271 else
272
273 return memcpy_ASM(dst, src, count);
274}
275