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21#ifndef __ASM_PPC_FSL_IFC_H
22#define __ASM_PPC_FSL_IFC_H
23
24#include <config.h>
25#include <common.h>
26
27
28
29
30#define CSPR_BA 0xFFFF0000
31#define CSPR_BA_SHIFT 16
32#define CSPR_PORT_SIZE 0x00000180
33#define CSPR_PORT_SIZE_SHIFT 7
34
35#define CSPR_PORT_SIZE_8 0x00000080
36
37#define CSPR_PORT_SIZE_16 0x00000100
38
39#define CSPR_PORT_SIZE_32 0x00000180
40
41#define CSPR_WP 0x00000040
42#define CSPR_WP_SHIFT 6
43
44#define CSPR_MSEL 0x00000006
45#define CSPR_MSEL_SHIFT 1
46
47#define CSPR_MSEL_NOR 0x00000000
48
49#define CSPR_MSEL_NAND 0x00000002
50
51#define CSPR_MSEL_GPCM 0x00000004
52
53#define CSPR_V 0x00000001
54#define CSPR_V_SHIFT 0
55
56
57#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
58
59
60
61
62#define IFC_AMASK_MASK 0xFFFF0000
63#define IFC_AMASK_SHIFT 16
64#define IFC_AMASK(n) (IFC_AMASK_MASK << \
65 (__ilog2(n) - IFC_AMASK_SHIFT))
66
67
68
69
70
71#define CSOR_NAND_ECC_ENC_EN 0x80000000
72
73#define CSOR_NAND_ECC_MODE_4 0x00000000
74
75#define CSOR_NAND_ECC_MODE_8 0x10000000
76
77#define CSOR_NAND_ECC_DEC_EN 0x04000000
78
79#define CSOR_NAND_RAL_MASK 0x01800000
80#define CSOR_NAND_RAL_SHIFT 20
81#define CSOR_NAND_RAL_1 0x00000000
82#define CSOR_NAND_RAL_2 0x00800000
83#define CSOR_NAND_RAL_3 0x01000000
84#define CSOR_NAND_RAL_4 0x01800000
85
86#define CSOR_NAND_PGS_MASK 0x00180000
87#define CSOR_NAND_PGS_SHIFT 16
88#define CSOR_NAND_PGS_512 0x00000000
89#define CSOR_NAND_PGS_2K 0x00080000
90#define CSOR_NAND_PGS_4K 0x00100000
91
92#define CSOR_NAND_SPRZ_MASK 0x0000E000
93#define CSOR_NAND_SPRZ_SHIFT 13
94#define CSOR_NAND_SPRZ_16 0x00000000
95#define CSOR_NAND_SPRZ_64 0x00002000
96#define CSOR_NAND_SPRZ_128 0x00004000
97#define CSOR_NAND_SPRZ_210 0x00006000
98#define CSOR_NAND_SPRZ_218 0x00008000
99#define CSOR_NAND_SPRZ_224 0x0000A000
100
101#define CSOR_NAND_PB_MASK 0x00000700
102#define CSOR_NAND_PB_SHIFT 8
103#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
104
105#define CSOR_NAND_TRHZ_MASK 0x0000001C
106#define CSOR_NAND_TRHZ_SHIFT 2
107#define CSOR_NAND_TRHZ_20 0x00000000
108#define CSOR_NAND_TRHZ_40 0x00000004
109#define CSOR_NAND_TRHZ_60 0x00000008
110#define CSOR_NAND_TRHZ_80 0x0000000C
111#define CSOR_NAND_TRHZ_100 0x00000010
112
113#define CSOR_NAND_BCTLD 0x00000001
114
115
116
117
118
119#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
120
121#define CSOR_NOR_PGRD_EN 0x10000000
122
123#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
124
125#define CSOR_NOR_ADM_MASK 0x0003E000
126#define CSOR_NOR_ADM_SHIFT_SHIFT 13
127#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
128
129#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
130#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
131
132#define CSOR_NOR_TRHZ_MASK 0x0000001C
133#define CSOR_NOR_TRHZ_SHIFT 2
134#define CSOR_NOR_TRHZ_20 0x00000000
135#define CSOR_NOR_TRHZ_40 0x00000004
136#define CSOR_NOR_TRHZ_60 0x00000008
137#define CSOR_NOR_TRHZ_80 0x0000000C
138#define CSOR_NOR_TRHZ_100 0x00000010
139
140#define CSOR_NOR_BCTLD 0x00000001
141
142
143
144
145
146#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
147
148#define CSOR_GPCM_GPMODE_ASIC 0x80000000
149
150#define CSOR_GPCM_PARITY_EVEN 0x40000000
151
152#define CSOR_GPCM_PAR_EN 0x20000000
153
154#define CSOR_GPCM_GPTO_MASK 0x0F000000
155#define CSOR_GPCM_GPTO_SHIFT 24
156#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
157
158#define CSOR_GPCM_RGETA_EXT 0x00080000
159
160#define CSOR_GPCM_WGETA_EXT 0x00040000
161
162#define CSOR_GPCM_ADM_MASK 0x0003E000
163#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
164#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
165
166#define CSOR_GPCM_GAPERRD_MASK 0x00000180
167#define CSOR_GPCM_GAPERRD_SHIFT 7
168#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
169
170#define CSOR_GPCM_TRHZ_MASK 0x0000001C
171#define CSOR_GPCM_TRHZ_20 0x00000000
172#define CSOR_GPCM_TRHZ_40 0x00000004
173#define CSOR_GPCM_TRHZ_60 0x00000008
174#define CSOR_GPCM_TRHZ_80 0x0000000C
175#define CSOR_GPCM_TRHZ_100 0x00000010
176
177#define CSOR_GPCM_BCTLD 0x00000001
178
179
180
181
182
183
184
185#define FTIM0_NAND 0x7EFF3F3F
186#define FTIM0_NAND_TCCST_SHIFT 25
187#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
188#define FTIM0_NAND_TWP_SHIFT 16
189#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
190#define FTIM0_NAND_TWCHT_SHIFT 8
191#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
192#define FTIM0_NAND_TWH_SHIFT 0
193#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
194
195
196
197#define FTIM1_NAND 0xFFFF3FFF
198#define FTIM1_NAND_TADLE_SHIFT 24
199#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
200#define FTIM1_NAND_TWBE_SHIFT 16
201#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
202#define FTIM1_NAND_TRR_SHIFT 8
203#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
204#define FTIM1_NAND_TRP_SHIFT 0
205#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
206
207
208
209#define FTIM2_NAND 0x1FE1F8FF
210#define FTIM2_NAND_TRAD_SHIFT 21
211#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
212#define FTIM2_NAND_TREH_SHIFT 11
213#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
214#define FTIM2_NAND_TWHRE_SHIFT 0
215#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
216
217
218
219#define FTIM3_NAND 0xFF000000
220#define FTIM3_NAND_TWW_SHIFT 24
221#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
222
223
224
225
226#define FTIM0_NOR 0xF03F3F3F
227#define FTIM0_NOR_TACSE_SHIFT 28
228#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
229#define FTIM0_NOR_TEADC_SHIFT 16
230#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
231#define FTIM0_NOR_TAVDS_SHIFT 8
232#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
233#define FTIM0_NOR_TEAHC_SHIFT 0
234#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
235
236
237
238#define FTIM1_NOR 0xFF003F3F
239#define FTIM1_NOR_TACO_SHIFT 24
240#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
241#define FTIM1_NOR_TRAD_NOR_SHIFT 8
242#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
243#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
244#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
245
246
247
248#define FTIM2_NOR 0x0F3CFCFF
249#define FTIM2_NOR_TCS_SHIFT 24
250#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
251#define FTIM2_NOR_TCH_SHIFT 18
252#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
253#define FTIM2_NOR_TWPH_SHIFT 10
254#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
255#define FTIM2_NOR_TWP_SHIFT 0
256#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
257
258
259
260
261#define FTIM0_GPCM 0xF03F3F3F
262#define FTIM0_GPCM_TACSE_SHIFT 28
263#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
264#define FTIM0_GPCM_TEADC_SHIFT 16
265#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
266#define FTIM0_GPCM_TAVDS_SHIFT 8
267#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
268#define FTIM0_GPCM_TEAHC_SHIFT 0
269#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
270
271
272
273#define FTIM1_GPCM 0xFF003F00
274#define FTIM1_GPCM_TACO_SHIFT 24
275#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
276#define FTIM1_GPCM_TRAD_SHIFT 8
277#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
278
279
280
281#define FTIM2_GPCM 0x0F3C00FF
282#define FTIM2_GPCM_TCS_SHIFT 24
283#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
284#define FTIM2_GPCM_TCH_SHIFT 18
285#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
286#define FTIM2_GPCM_TWP_SHIFT 0
287#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
288
289
290
291
292
293#define IFC_RB_STAT_READY_CS0 0x80000000
294#define IFC_RB_STAT_READY_CS1 0x40000000
295#define IFC_RB_STAT_READY_CS2 0x20000000
296#define IFC_RB_STAT_READY_CS3 0x10000000
297
298
299
300
301#define IFC_GCR_MASK 0x8000F800
302
303#define IFC_GCR_SOFT_RST_ALL 0x80000000
304
305#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
306#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
307
308
309
310
311
312#define IFC_CM_EVTER_STAT_CSER 0x80000000
313
314
315
316
317
318#define IFC_CM_EVTER_EN_CSEREN 0x80000000
319
320
321
322
323
324#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
325
326
327
328
329
330#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
331#define IFC_CM_ERATTR0_ERAID 0x0FF00000
332#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
333
334
335
336
337#define IFC_CCR_MASK 0x0F0F8800
338
339#define IFC_CCR_CLK_DIV_MASK 0x0F000000
340#define IFC_CCR_CLK_DIV_SHIFT 24
341#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
342
343#define IFC_CCR_CLK_DLY_MASK 0x000F0000
344#define IFC_CCR_CLK_DLY_SHIFT 16
345#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
346
347#define IFC_CCR_INV_CLK_EN 0x00008000
348
349#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
350
351
352
353
354
355#define IFC_CSR_CLK_STAT_STABLE 0x80000000
356
357
358
359
360
361
362
363
364#define IFC_NAND_NCFGR_BOOT 0x80000000
365
366#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
367
368#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
369
370#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
371#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
372#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
373
374#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
375#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
376
377
378
379
380
381#define IFC_NAND_FCR0_CMD0 0xFF000000
382#define IFC_NAND_FCR0_CMD0_SHIFT 24
383#define IFC_NAND_FCR0_CMD1 0x00FF0000
384#define IFC_NAND_FCR0_CMD1_SHIFT 16
385#define IFC_NAND_FCR0_CMD2 0x0000FF00
386#define IFC_NAND_FCR0_CMD2_SHIFT 8
387#define IFC_NAND_FCR0_CMD3 0x000000FF
388#define IFC_NAND_FCR0_CMD3_SHIFT 0
389#define IFC_NAND_FCR1_CMD4 0xFF000000
390#define IFC_NAND_FCR1_CMD4_SHIFT 24
391#define IFC_NAND_FCR1_CMD5 0x00FF0000
392#define IFC_NAND_FCR1_CMD5_SHIFT 16
393#define IFC_NAND_FCR1_CMD6 0x0000FF00
394#define IFC_NAND_FCR1_CMD6_SHIFT 8
395#define IFC_NAND_FCR1_CMD7 0x000000FF
396#define IFC_NAND_FCR1_CMD7_SHIFT 0
397
398
399
400
401
402#define IFC_NAND_COL_MS 0x80000000
403
404#define IFC_NAND_COL_CA_MASK 0x00000FFF
405
406
407
408
409
410#define IFC_NAND_BC 0x000001FF
411
412
413
414
415
416#define IFC_NAND_FIR0_OP0 0xFC000000
417#define IFC_NAND_FIR0_OP0_SHIFT 26
418#define IFC_NAND_FIR0_OP1 0x03F00000
419#define IFC_NAND_FIR0_OP1_SHIFT 20
420#define IFC_NAND_FIR0_OP2 0x000FC000
421#define IFC_NAND_FIR0_OP2_SHIFT 14
422#define IFC_NAND_FIR0_OP3 0x00003F00
423#define IFC_NAND_FIR0_OP3_SHIFT 8
424#define IFC_NAND_FIR0_OP4 0x000000FC
425#define IFC_NAND_FIR0_OP4_SHIFT 2
426#define IFC_NAND_FIR1_OP5 0xFC000000
427#define IFC_NAND_FIR1_OP5_SHIFT 26
428#define IFC_NAND_FIR1_OP6 0x03F00000
429#define IFC_NAND_FIR1_OP6_SHIFT 20
430#define IFC_NAND_FIR1_OP7 0x000FC000
431#define IFC_NAND_FIR1_OP7_SHIFT 14
432#define IFC_NAND_FIR1_OP8 0x00003F00
433#define IFC_NAND_FIR1_OP8_SHIFT 8
434#define IFC_NAND_FIR1_OP9 0x000000FC
435#define IFC_NAND_FIR1_OP9_SHIFT 2
436#define IFC_NAND_FIR2_OP10 0xFC000000
437#define IFC_NAND_FIR2_OP10_SHIFT 26
438#define IFC_NAND_FIR2_OP11 0x03F00000
439#define IFC_NAND_FIR2_OP11_SHIFT 20
440#define IFC_NAND_FIR2_OP12 0x000FC000
441#define IFC_NAND_FIR2_OP12_SHIFT 14
442#define IFC_NAND_FIR2_OP13 0x00003F00
443#define IFC_NAND_FIR2_OP13_SHIFT 8
444#define IFC_NAND_FIR2_OP14 0x000000FC
445#define IFC_NAND_FIR2_OP14_SHIFT 2
446
447
448
449
450
451enum ifc_nand_fir_opcodes {
452 IFC_FIR_OP_NOP,
453 IFC_FIR_OP_CA0,
454 IFC_FIR_OP_CA1,
455 IFC_FIR_OP_CA2,
456 IFC_FIR_OP_CA3,
457 IFC_FIR_OP_RA0,
458 IFC_FIR_OP_RA1,
459 IFC_FIR_OP_RA2,
460 IFC_FIR_OP_RA3,
461 IFC_FIR_OP_CMD0,
462 IFC_FIR_OP_CMD1,
463 IFC_FIR_OP_CMD2,
464 IFC_FIR_OP_CMD3,
465 IFC_FIR_OP_CMD4,
466 IFC_FIR_OP_CMD5,
467 IFC_FIR_OP_CMD6,
468 IFC_FIR_OP_CMD7,
469 IFC_FIR_OP_CW0,
470 IFC_FIR_OP_CW1,
471 IFC_FIR_OP_CW2,
472 IFC_FIR_OP_CW3,
473 IFC_FIR_OP_CW4,
474 IFC_FIR_OP_CW5,
475 IFC_FIR_OP_CW6,
476 IFC_FIR_OP_CW7,
477 IFC_FIR_OP_WBCD,
478 IFC_FIR_OP_RBCD,
479 IFC_FIR_OP_BTRD,
480 IFC_FIR_OP_RDSTAT,
481 IFC_FIR_OP_NWAIT,
482 IFC_FIR_OP_WFR,
483 IFC_FIR_OP_SBRD,
484 IFC_FIR_OP_UA,
485 IFC_FIR_OP_RB,
486};
487
488
489
490
491#define IFC_NAND_CSEL 0x0C000000
492#define IFC_NAND_CSEL_SHIFT 26
493#define IFC_NAND_CSEL_CS0 0x00000000
494#define IFC_NAND_CSEL_CS1 0x04000000
495#define IFC_NAND_CSEL_CS2 0x08000000
496#define IFC_NAND_CSEL_CS3 0x0C000000
497
498
499
500
501
502#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
503
504#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
505
506#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
507
508#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
509
510#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
511
512#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
513
514
515
516
517
518#define IFC_NAND_EVTER_STAT_OPC 0x80000000
519
520#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
521
522#define IFC_NAND_EVTER_STAT_WPER 0x04000000
523
524#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
525
526#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
527
528#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
529
530#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
531
532
533
534
535
536#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
537
538#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
539
540#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
541
542#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
543
544
545
546
547
548#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
549
550#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
551
552#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
553
554#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
555
556#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
557
558
559
560
561
562#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
563
564#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
565
566#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
567
568#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
569
570#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
571
572
573
574
575#define IFC_NAND_ERATTR0_MASK 0x0C080000
576
577#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
578#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
579#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
580#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
581
582#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
583
584
585
586
587
588#define IFC_NAND_NFSR_RS0 0xFF000000
589
590#define IFC_NAND_NFSR_RS1 0x00FF0000
591
592
593
594
595
596#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
597#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
598#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
599#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
600#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
601#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
602#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
603#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
604#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
605#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
606#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
607#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
608#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
609#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
610#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
611#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
612#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
613#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
614#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
615#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
616#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
617#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
618#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
619#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
620#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
621#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
622#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
623#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
624#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
625#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
626#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
627#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
628
629
630
631
632#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
633#define IFC_NAND_NCR_FTOCNT_SHIFT 25
634#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
635
636
637
638
639
640#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
641
642#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
643
644
645
646
647
648#define IFC_NAND_MDR_RDATA0 0xFF000000
649
650#define IFC_NAND_MDR_RDATA1 0x00FF0000
651
652
653
654
655
656
657
658
659#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
660
661#define IFC_NOR_EVTER_STAT_WPER 0x04000000
662
663#define IFC_NOR_EVTER_STAT_STOER 0x01000000
664
665
666
667
668
669#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
670
671#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
672
673#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
674
675
676
677
678
679#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
680
681#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
682
683#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
684
685
686
687
688
689#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
690
691#define IFC_NOR_ERATTR0_ERAID 0x000FF000
692
693#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
694#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
695#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
696#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
697
698#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
699
700
701
702
703#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
704#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
705
706
707
708
709#define IFC_NORCR_MASK 0x0F0F0000
710
711#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
712#define IFC_NORCR_NUM_PHASE_SHIFT 24
713#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
714
715#define IFC_NORCR_STOCNT_MASK 0x000F0000
716#define IFC_NORCR_STOCNT_SHIFT 16
717#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
718
719
720
721
722
723
724
725
726#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
727
728#define IFC_GPCM_EVTER_STAT_PER 0x01000000
729
730
731
732
733
734#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
735
736#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
737
738
739
740
741
742#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
743
744#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
745
746
747
748
749
750#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
751
752#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
753
754#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
755#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
756#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
757#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
758
759#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
760
761
762
763
764
765#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
766
767#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
768
769#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
770
771
772
773
774#define IFC_GPCM_STAT_BSY 0x80000000
775
776
777#ifndef __ASSEMBLY__
778#include <asm/io.h>
779
780extern void print_ifc_regs(void);
781extern void init_early_memctl_regs(void);
782
783#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
784
785#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
786#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
787#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
788#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
789
790#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
791#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
792#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
793#define set_ifc_ftim(i, j, v) \
794 (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
795
796#define FSL_IFC_BANK_COUNT 4
797
798enum ifc_chip_sel {
799 IFC_CS0,
800 IFC_CS1,
801 IFC_CS2,
802 IFC_CS3,
803};
804
805enum ifc_ftims {
806 IFC_FTIM0,
807 IFC_FTIM1,
808 IFC_FTIM2,
809 IFC_FTIM3,
810};
811
812
813
814
815struct fsl_ifc_nand {
816 u32 ncfgr;
817 u32 res1[0x4];
818 u32 nand_fcr0;
819 u32 nand_fcr1;
820 u32 res2[0x8];
821 u32 row0;
822 u32 res3;
823 u32 col0;
824 u32 res4;
825 u32 row1;
826 u32 res5;
827 u32 col1;
828 u32 res6;
829 u32 row2;
830 u32 res7;
831 u32 col2;
832 u32 res8;
833 u32 row3;
834 u32 res9;
835 u32 col3;
836 u32 res10[0x24];
837 u32 nand_fbcr;
838 u32 res11;
839 u32 nand_fir0;
840 u32 nand_fir1;
841 u32 nand_fir2;
842 u32 res12[0x10];
843 u32 nand_csel;
844 u32 res13;
845 u32 nandseq_strt;
846 u32 res14;
847 u32 nand_evter_stat;
848 u32 res15;
849 u32 pgrdcmpl_evt_stat;
850 u32 res16[0x2];
851 u32 nand_evter_en;
852 u32 res17[0x2];
853 u32 nand_evter_intr_en;
854 u32 res18[0x2];
855 u32 nand_erattr0;
856 u32 nand_erattr1;
857 u32 res19[0x10];
858 u32 nand_fsr;
859 u32 res20;
860 u32 nand_eccstat0;
861 u32 nand_eccstat1;
862 u32 nand_eccstat2;
863 u32 nand_eccstat3;
864 u32 res21[0x20];
865 u32 nanndcr;
866 u32 res22[0x2];
867 u32 nand_autoboot_trgr;
868 u32 res23;
869 u32 nand_mdr;
870 u32 res24[0x5C];
871};
872
873
874
875
876struct fsl_ifc_nor {
877 u32 nor_evter_stat;
878 u32 res1[0x2];
879 u32 nor_evter_en;
880 u32 res2[0x2];
881 u32 nor_evter_intr_en;
882 u32 res3[0x2];
883 u32 nor_erattr0;
884 u32 nor_erattr1;
885 u32 nor_erattr2;
886 u32 res4[0x4];
887 u32 norcr;
888 u32 res5[0xEF];
889};
890
891
892
893
894struct fsl_ifc_gpcm {
895 u32 gpcm_evter_stat;
896 u32 res1[0x2];
897 u32 gpcm_evter_en;
898 u32 res2[0x2];
899 u32 gpcm_evter_intr_en;
900 u32 res3[0x2];
901 u32 gpcm_erattr0;
902 u32 gpcm_erattr1;
903 u32 gpcm_erattr2;
904 u32 gpcm_stat;
905 u32 res4[0x1F3];
906};
907
908
909
910
911
912struct fsl_ifc {
913 u32 ifc_rev;
914 u32 res1[0x3];
915 struct {
916 u32 cspr;
917 u32 res2[0x2];
918 } cspr_cs[FSL_IFC_BANK_COUNT];
919 u32 res3[0x18];
920 struct {
921 u32 amask;
922 u32 res4[0x2];
923 } amask_cs[FSL_IFC_BANK_COUNT];
924 u32 res5[0x18];
925 struct {
926 u32 csor;
927 u32 res6[0x2];
928 } csor_cs[FSL_IFC_BANK_COUNT];
929 u32 res7[0x18];
930 struct {
931 u32 ftim[4];
932 u32 res8[0x8];
933 } ftim_cs[FSL_IFC_BANK_COUNT];
934 u32 res9[0x60];
935 u32 rb_stat;
936 u32 res10[0x2];
937 u32 ifc_gcr;
938 u32 res11[0x2];
939 u32 cm_evter_stat;
940 u32 res12[0x2];
941 u32 cm_evter_en;
942 u32 res13[0x2];
943 u32 cm_evter_intr_en;
944 u32 res14[0x2];
945 u32 cm_erattr0;
946 u32 cm_erattr1;
947 u32 res15[0x2];
948 u32 ifc_ccr;
949 u32 ifc_csr;
950 u32 res16[0x2EB];
951 struct fsl_ifc_nand ifc_nand;
952 struct fsl_ifc_nor ifc_nor;
953 struct fsl_ifc_gpcm ifc_gpcm;
954};
955
956#endif
957#endif
958