LXR uboot/board/RPXlite/RPXlite.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  26 * U-Boot port on RPXlite board
  27 *
  28 * DRAM related UPMA register values are modified.
  29 * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
  30 */
  31
  32#include <common.h>
  33#include <mpc8xx.h>
  34
  35/* ------------------------------------------------------------------------- */
  36
  37static long int dram_size (long int, long int *, long int);
  38
  39/* ------------------------------------------------------------------------- */
  40
  41#define _NOT_USED_      0xFFFFCC25
  42
  43const uint sdram_table[] = {
  44        /*
  45         * Single Read. (Offset 00h in UPMA RAM)
  46         */
  47        0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
  48        0x3FBFCC27,             /* last */
  49        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  50
  51        /*
  52         * Burst Read. (Offset 08h in UPMA RAM)
  53         */
  54        0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
  55        0x3FBFCC27,             /* last */
  56        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  58        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  59
  60        /*
  61         * Single Write. (Offset 18h in UPMA RAM)
  62         */
  63        0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
  64        0x3FFFCC27,             /* last */
  65        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66
  67        /*
  68         * Burst Write. (Offset 20h in UPMA RAM)
  69         */
  70        0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
  71        0x0CFFCC00, 0x33FFCC27, /* last */
  72        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  74        _NOT_USED_, _NOT_USED_,
  75
  76        /*
  77         * Refresh. (Offset 30h in UPMA RAM)
  78         */
  79        0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
  80        0x3FFFCC27,             /* last */
  81        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  83
  84        /*
  85         * Exception. (Offset 3Ch in UPMA RAM)
  86         */
  87        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
  88};
  89
  90/* ------------------------------------------------------------------------- */
  91
  92
  93/*
  94 * Check Board Identity:
  95 */
  96
  97int checkboard (void)
  98{
  99        puts ("Board: RPXlite\n");
 100        return (0);
 101}
 102
 103/* ------------------------------------------------------------------------- */
 104
 105phys_size_t initdram (int board_type)
 106{
 107        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 108        volatile memctl8xx_t *memctl = &immap->im_memctl;
 109        long int size10;
 110
 111        upmconfig (UPMA, (uint *) sdram_table,
 112                   sizeof (sdram_table) / sizeof (uint));
 113
 114        /* Refresh clock prescalar */
 115        memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 116
 117        memctl->memc_mar = 0x00000000;
 118
 119        /* Map controller banks 1 to the SDRAM bank */
 120        memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 121        memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 122
 123        memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));     /* no refresh yet */
 124
 125        udelay (200);
 126
 127        /* perform SDRAM initializsation sequence */
 128
 129        memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - refresh twice */
 130        udelay (1);
 131
 132        memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 133
 134        udelay (1000);
 135
 136        /* Check Bank 0 Memory Size
 137         * try 10 column mode
 138         */
 139
 140        size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 141                            SDRAM_MAX_SIZE);
 142
 143        return (size10);
 144}
 145
 146/* ------------------------------------------------------------------------- */
 147
 148/*
 149 * Check memory range for valid RAM. A simple memory test determines
 150 * the actually available RAM size between addresses `base' and
 151 * `base + maxsize'. Some (not all) hardware errors are detected:
 152 * - short between address lines
 153 * - short between data lines
 154 */
 155
 156static long int dram_size (long int mamr_value, long int *base,
 157                           long int maxsize)
 158{
 159        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 160        volatile memctl8xx_t *memctl = &immap->im_memctl;
 161
 162        memctl->memc_mamr = mamr_value;
 163
 164        return (get_ram_size (base, maxsize));
 165}
 166