LXR uboot/board/csb472/csb472.c

   1/*
   2 * (C) Copyright 2004
   3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/processor.h>
  26#include <i2c.h>
  27#include <miiphy.h>
  28#include <asm/ppc4xx-emac.h>
  29
  30void sdram_init(void);
  31
  32/*
  33 * board_early_init_f: do early board initialization
  34 *
  35 */
  36int board_early_init_f(void)
  37{
  38   /*-------------------------------------------------------------------------+
  39   | Interrupt controller setup for the Walnut board.
  40   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
  41   |       IRQ 16    405GP internally generated; active low; level sensitive
  42   |       IRQ 17-24 RESERVED
  43   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  44   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  45   |       IRQ 27 (EXT IRQ 2) Not Used
  46   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  47   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  48   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  49   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  50   | Note for Walnut board:
  51   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
  52   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
  53   |       interrupt. The FPGA must be read to determine which device
  54   |       caused the interrupt. The default setting of the FPGA clears
  55   |
  56   +-------------------------------------------------------------------------*/
  57
  58        mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  59        mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
  60        mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
  61        mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
  62        mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
  63        mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
  64        mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  65
  66        mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
  67
  68        return 0; /* success */
  69}
  70
  71/*
  72 * checkboard: identify/verify the board we are running
  73 *
  74 * Remark: we just assume it is correct board here!
  75 *
  76 */
  77int checkboard(void)
  78{
  79        printf("BOARD: Cogent CSB472\n");
  80
  81        return 0; /* success */
  82}
  83
  84/*
  85 * initram: Determine the size of mounted DRAM
  86 *
  87 * Size is determined by reading SDRAM configuration registers as
  88 * configured by initialization code
  89 *
  90 */
  91phys_size_t initdram (int board_type)
  92{
  93        ulong tot_size;
  94        ulong bank_size;
  95        ulong tmp;
  96
  97        /*
  98         * ToDo: Move the asm init routine sdram_init() to this C file,
  99         * or even better use some common ppc4xx code available
 100         * in arch/powerpc/cpu/ppc4xx
 101         */
 102        sdram_init();
 103
 104        tot_size = 0;
 105
 106        mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 107        tmp = mfdcr (SDRAM0_CFGDATA);
 108        if (tmp & 0x00000001) {
 109                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 110                tot_size += bank_size;
 111        }
 112
 113        mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 114        tmp = mfdcr (SDRAM0_CFGDATA);
 115        if (tmp & 0x00000001) {
 116                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 117                tot_size += bank_size;
 118        }
 119
 120        mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 121        tmp = mfdcr (SDRAM0_CFGDATA);
 122        if (tmp & 0x00000001) {
 123                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 124                tot_size += bank_size;
 125        }
 126
 127        mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 128        tmp = mfdcr (SDRAM0_CFGDATA);
 129        if (tmp & 0x00000001) {
 130                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 131                tot_size += bank_size;
 132        }
 133
 134        return tot_size;
 135}
 136
 137/*
 138 * last_stage_init: final configurations (such as PHY etc)
 139 *
 140 */
 141int last_stage_init(void)
 142{
 143        /* initialize the PHY */
 144        miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 145
 146        /* AUTO neg */
 147        miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
 148                        BMCR_ANENABLE | BMCR_ANRESTART);
 149
 150        /* LEDs     */
 151        miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 152
 153        return 0; /* success */
 154}
 155