uboot/board/ep8260/ep8260.c
<<
>>
Prefs 
   1/*
   2 * (C) Copyright 2001, 2002
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2002
   6 * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <ioports.h>
  29#include <mpc8260.h>
  30#include "ep8260.h"
  31/*
  32 * I/O Port configuration table
  33 *
  34 * if conf is 1, then that port pin will be configured at boot time
  35 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  36 */
  37
  38const iop_conf_t iop_conf_tab[4][32] = {
  39
  40    /* Port A configuration */
  41    {   /*            conf ppar psor pdir podr pdat */
  42        /* PA31 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  43        /* PA30 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  44        /* PA29 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  45        /* PA28 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  46        /* PA27 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  47        /* PA26 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  48        /* PA25 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  49        /* PA24 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  50        /* PA23 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  51        /* PA22 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  52        /* PA21 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  53        /* PA20 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  54        /* PA19 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  55        /* PA18 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  56        /* PA17 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  57        /* PA16 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  58        /* PA15 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  59        /* PA14 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  60        /* PA13 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  61        /* PA12 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  62        /* PA11 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  63        /* PA10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
  64        /* PA9  */ {   0,   1,   0,   1,   0,   0   }, /*  */
  65        /* PA8  */ {   0,   1,   0,   0,   0,   0   }, /*  */
  66        /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  67        /* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
  68        /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  69        /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  70        /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  71        /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  72        /* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
  73        /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  74    },
  75
  76    /* Port B configuration */
  77    {   /*            conf ppar psor pdir podr pdat */
  78        /* PB31 */ {   0,   1,   0,   1,   0,   0   }, /*  */
  79        /* PB30 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  80        /* PB29 */ {   0,   1,   1,   1,   0,   0   }, /*  */
  81        /* PB28 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  82        /* PB27 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  83        /* PB26 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  84        /* PB25 */ {   0,   1,   0,   1,   0,   0   }, /*  */
  85        /* PB24 */ {   0,   1,   0,   1,   0,   0   }, /*  */
  86        /* PB23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
  87        /* PB22 */ {   0,   1,   0,   1,   0,   0   }, /*  */
  88        /* PB21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  89        /* PB20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  90        /* PB19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  91        /* PB18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
  92        /* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
  93        /* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
  94        /* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
  95        /* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
  96        /* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
  97        /* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
  98        /* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
  99        /* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
 100        /* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
 101        /* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
 102        /* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
 103        /* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
 104        /* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
 105        /* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
 106        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 107        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 108        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 109        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 110    },
 111
 112    /* Port C */
 113    {   /*            conf ppar psor pdir podr pdat */
 114        /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 115        /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 116        /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /*  */
 117        /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 118        /* PC27 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
 119        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 120        /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 121        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 122        /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
 123        /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 124        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 125        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 126        /* PC19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 127        /* PC18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 128        /* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK15 */
 129        /* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK16 */
 130        /* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
 131        /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 132        /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 133        /* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
 134        /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
 135        /* PC10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
 136        /* PC9  */ {   0,   0,   0,   1,   0,   0   }, /*  */
 137        /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 138        /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 139        /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 140        /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 141        /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 142        /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 143        /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /*  */
 144        /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /*  */
 145        /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /*  */
 146    },
 147
 148    /* Port D */
 149    {   /*            conf ppar psor pdir podr pdat */
 150        /* PD31 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 151        /* PD30 */ {   0,   1,   1,   1,   0,   0   }, /*  */
 152        /* PD29 */ {   0,   1,   0,   1,   0,   0   }, /*  */
 153        /* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
 154        /* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
 155        /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 156        /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 157        /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 158        /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 159        /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 160        /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 161        /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 162        /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 163        /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 164        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /*  */
 165        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /*  */
 166        /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 167        /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 168        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 169        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 170        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 171        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 172        /* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 173        /* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 174        /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 175        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 176        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 177        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 178        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 179        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 180        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 181        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 182    }
 183};
 184
 185/* ------------------------------------------------------------------------- */
 186
 187/*
 188 * Setup CS4 to enable the Board Control/Status registers.
 189 * Otherwise the smcs won't work.
 190*/
 191int board_early_init_f (void)
 192{
 193        volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
 194        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 195        volatile memctl8260_t *memctl = &immap->im_memctl;
 196
 197        memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 198        memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 199        regs->bcsr1 = 0x62;     /* to enable terminal on SMC1 */
 200        regs->bcsr2 = 0x30;     /* enable NVRAM and writing FLASH */
 201        return 0;
 202}
 203
 204void reset_phy (void)
 205{
 206        volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
 207
 208        regs->bcsr4 = 0xC0;
 209}
 210
 211/*
 212 * Check Board Identity:
 213 * I don' know, how the next board revisions will be coded.
 214 * Thats why its a static interpretation ...
 215*/
 216
 217int checkboard (void)
 218{
 219        volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
 220        uint major = 0, minor = 0;
 221
 222        switch (regs->bcsr0) {
 223        case 0x02:
 224                major = 1;
 225                break;
 226        case 0x03:
 227                major = 1;
 228                minor = 1;
 229                break;
 230        case 0x06:
 231                major = 1;
 232                minor = 3;
 233                break;
 234        default:
 235                break;
 236        }
 237        printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
 238                major, minor);
 239        return 0;
 240}
 241
 242
 243/* ------------------------------------------------------------------------- */
 244
 245
 246phys_size_t initdram (int board_type)
 247{
 248        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 249        volatile memctl8260_t *memctl = &immap->im_memctl;
 250        volatile uchar c = 0;
 251        volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
 252
 253/*
 254        ulong psdmr = CONFIG_SYS_PSDMR;
 255#ifdef CONFIG_SYS_LSDRAM
 256        ulong lsdmr = CONFIG_SYS_LSDMR;
 257#endif
 258*/
 259        long size = CONFIG_SYS_SDRAM0_SIZE;
 260        int i;
 261
 262
 263/*
 264* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 265*
 266* "At system reset, initialization software must set up the
 267*  programmable parameters in the memory controller banks registers
 268*  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 269*  system software should execute the following initialization sequence
 270*  for each SDRAM device.
 271*
 272*  1. Issue a PRECHARGE-ALL-BANKS command
 273*  2. Issue eight CBR REFRESH commands
 274*  3. Issue a MODE-SET command to initialize the mode register
 275*
 276*  The initial commands are executed by setting P/LSDMR[OP] and
 277*  accessing the SDRAM with a single-byte transaction."
 278*
 279* The appropriate BRx/ORx registers have already been set when we
 280* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 281*/
 282
 283        memctl->memc_psrt = CONFIG_SYS_PSRT;
 284        memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 285
 286        memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
 287        *ramaddr = c;
 288
 289        memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
 290        for (i = 0; i < 8; i++)
 291                *ramaddr = c;
 292
 293        memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
 294        *ramaddr = c;
 295
 296        memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
 297        *ramaddr = c;
 298
 299#ifndef CONFIG_SYS_RAMBOOT
 300#ifdef CONFIG_SYS_LSDRAM
 301        size += CONFIG_SYS_SDRAM1_SIZE;
 302        ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
 303        memctl->memc_lsrt = CONFIG_SYS_LSRT;
 304
 305        memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
 306        *ramaddr = c;
 307
 308        memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
 309        for (i = 0; i < 8; i++)
 310                *ramaddr = c;
 311
 312        memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
 313        *ramaddr = c;
 314
 315        memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
 316        *ramaddr = c;
 317#endif /* CONFIG_SYS_LSDRAM */
 318#endif /* CONFIG_SYS_RAMBOOT */
 319        return (size * 1024 * 1024);
 320}
 321
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.