1/*------------------------------------------------------------------------------+ */ 2/* */ 3/* This source code is dual-licensed. You may use it under the terms */ 4/* of the GNU General Public License version 2, or under the license */ 5/* below. */ 6/* */ 7/* This source code has been made available to you by IBM on an AS-IS */ 8/* basis. Anyone receiving this source is licensed under IBM */ 9/* copyrights to use it in any way he or she deems fit, including */ 10/* copying it, modifying it, compiling it, and redistributing it either */ 11/* with or without modifications. No license under IBM patents or */ 12/* patent applications is to be implied by the copyright license. */ 13/* */ 14/* Any user of this software should understand that IBM cannot provide */ 15/* technical support for this software and will not be responsible for */ 16/* any consequences resulting from the use of this software. */ 17/* */ 18/* Any person who transfers this source code or any derivative work */ 19/* must include the IBM copyright notice, this paragraph, and the */ 20/* preceding two paragraphs in the transferred software. */ 21/* */ 22/* COPYRIGHT I B M CORPORATION 1995 */ 23/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ 24/*------------------------------------------------------------------------------- */ 25 26/*----------------------------------------------------------------------------- */ 27/* Function: ext_bus_cntlr_init */ 28/* Description: Initializes the External Bus Controller for the external */ 29/* peripherals. IMPORTANT: For pass1 this code must run from */ 30/* cache since you can not reliably change a peripheral banks */ 31/* timing register (pbxap) while running code from that bank. */ 32/* For ex., since we are running from ROM on bank 0, we can NOT */ 33/* execute the code that modifies bank 0 timings from ROM, so */ 34/* we run it from cache. */ 35/* Bank 0 - Flash and SRAM */ 36/* Bank 1 - NVRAM/RTC */ 37/* Bank 2 - Keyboard/Mouse controller */ 38/* Bank 3 - IR controller */ 39/* Bank 4 - not used */ 40/* Bank 5 - not used */ 41/* Bank 6 - not used */ 42/* Bank 7 - FPGA registers */ 43/*----------------------------------------------------------------------------- */ 44#include <asm/ppc4xx.h> 45 46#include <ppc_asm.tmpl> 47#include <ppc_defs.h> 48 49#include <asm/cache.h> 50#include <asm/mmu.h> 51 52 53 .globl write_without_sync 54write_without_sync: 55 /* 56 * Write one values to host via pci busmastering 57 * ptr = 0xc0000000 -> 0x01000000 (PCI) 58 * *ptr = 0x01234567; 59 */ 60 addi r31,0,0 61 lis r31,0xc000 62 63start1: 64 lis r0,0x0123 65 ori r0,r0,0x4567 66 stw r0,0(r31) 67 68 /* 69 * Read one value back 70 * ptr = (volatile unsigned long *)addr; 71 * val = *ptr; 72 */ 73 74 lwz r0,0(r31) 75 76 /* 77 * One pci config write 78 * ibmPciConfigWrite(0x2e, 2, 0x1234); 79 */ 80 /* subsystem id */ 81 82 li r4,0x002C 83 oris r4,r4,0x8000 84 lis r3,0xEEC0 85 stwbrx r4,0,r3 86 87 li r5,0x1234 88 ori r3,r3,0x4 89 stwbrx r5,0,r3 90 91 b start1 92 93 blr /* never reached !!!! */ 94 95 .globl write_with_sync 96write_with_sync: 97 /* 98 * Write one values to host via pci busmastering 99 * ptr = 0xc0000000 -> 0x01000000 (PCI) 100 * *ptr = 0x01234567; 101 */ 102 addi r31,0,0 103 lis r31,0xc000 104 105start2: 106 lis r0,0x0123 107 ori r0,r0,0x4567 108 stw r0,0(r31) 109 110 /* 111 * Read one value back 112 * ptr = (volatile unsigned long *)addr; 113 * val = *ptr; 114 */ 115 116 lwz r0,0(r31) 117 118 /* 119 * One pci config write 120 * ibmPciConfigWrite(0x2e, 2, 0x1234); 121 */ 122 /* subsystem id */ 123 124 li r4,0x002C 125 oris r4,r4,0x8000 126 lis r3,0xEEC0 127 stwbrx r4,0,r3 128 sync 129 130 li r5,0x1234 131 ori r3,r3,0x4 132 stwbrx r5,0,r3 133 sync 134 135 b start2 136 137 blr /* never reached !!!! */ 138 139 .globl write_with_less_sync 140write_with_less_sync: 141 /* 142 * Write one values to host via pci busmastering 143 * ptr = 0xc0000000 -> 0x01000000 (PCI) 144 * *ptr = 0x01234567; 145 */ 146 addi r31,0,0 147 lis r31,0xc000 148 149start2b: 150 lis r0,0x0123 151 ori r0,r0,0x4567 152 stw r0,0(r31) 153 154 /* 155 * Read one value back 156 * ptr = (volatile unsigned long *)addr; 157 * val = *ptr; 158 */ 159 160 lwz r0,0(r31) 161 162 /* 163 * One pci config write 164 * ibmPciConfigWrite(0x2e, 2, 0x1234); 165 */ 166 /* subsystem id */ 167 168 li r4,0x002C 169 oris r4,r4,0x8000 170 lis r3,0xEEC0 171 stwbrx r4,0,r3 172 sync 173 174 li r5,0x1234 175 ori r3,r3,0x4 176 stwbrx r5,0,r3 177/* sync */ 178 179 b start2b 180 181 blr /* never reached !!!! */ 182 183 .globl write_with_more_sync 184write_with_more_sync: 185 /* 186 * Write one values to host via pci busmastering 187 * ptr = 0xc0000000 -> 0x01000000 (PCI) 188 * *ptr = 0x01234567; 189 */ 190 addi r31,0,0 191 lis r31,0xc000 192 193start3: 194 lis r0,0x0123 195 ori r0,r0,0x4567 196 stw r0,0(r31) 197 sync 198 199 /* 200 * Read one value back 201 * ptr = (volatile unsigned long *)addr; 202 * val = *ptr; 203 */ 204 205 lwz r0,0(r31) 206 sync 207 208 /* 209 * One pci config write 210 * ibmPciConfigWrite(0x2e, 2, 0x1234); 211 */ 212 /* subsystem id (PCIC0_SBSYSVID)*/ 213 214 li r4,0x002C 215 oris r4,r4,0x8000 216 lis r3,0xEEC0 217 stwbrx r4,0,r3 218 sync 219 220 li r5,0x1234 221 ori r3,r3,0x4 222 stwbrx r5,0,r3 223 sync 224 225 b start3 226 227 blr /* never reached !!!! */ 228