uboot/board/etin/kvme080/kvme080.c
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   1/*
   2 * (C) Copyright 2005
   3 * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <mpc824x.h>
  26#include <pci.h>
  27#include <i2c.h>
  28#include <netdev.h>
  29#include <asm/processor.h>
  30#include <asm/mmu.h>
  31
  32int checkboard(void)
  33{
  34        puts ("Board: KVME080\n");
  35        return 0;
  36}
  37
  38unsigned long setdram(int m, int row, int col, int bank)
  39{
  40        int i;
  41        unsigned long start, end;
  42        uint32_t mccr1;
  43        uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
  44        uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
  45        uint8_t mber = 0;
  46
  47        CONFIG_READ_WORD(MCCR1, mccr1);
  48        mccr1 &= 0xffff0000;
  49
  50        start = CONFIG_SYS_SDRAM_BASE;
  51        end = start + (1 << (col + row + 3) ) * bank - 1;
  52
  53        for (i = 0; i < m; i++) {
  54                mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
  55                if (i < 4) {
  56                        msar1  |= ((start >> 20) & 0xff) << i * 8;
  57                        emsar1 |= ((start >> 28) & 0xff) << i * 8;
  58                        mear1  |= ((end >> 20) & 0xff) << i * 8;
  59                        emear1 |= ((end >> 28) & 0xff) << i * 8;
  60                } else {
  61                        msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
  62                        emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
  63                        mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
  64                        emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
  65                }
  66                mber |= 1 << i;
  67                start += (1 << (col + row + 3) ) * bank;
  68                end += (1 << (col + row + 3) ) * bank;
  69        }
  70        for (; i < 8; i++) {
  71                if (i < 4) {
  72                        msar1  |= 0xff << i * 8;
  73                        emsar1 |= 0x30 << i * 8;
  74                        mear1  |= 0xff << i * 8;
  75                        emear1 |= 0x30 << i * 8;
  76                } else {
  77                        msar2  |= 0xff << (i-4) * 8;
  78                        emsar2 |= 0x30 << (i-4) * 8;
  79                        mear2  |= 0xff << (i-4) * 8;
  80                        emear2 |= 0x30 << (i-4) * 8;
  81                }
  82        }
  83
  84        CONFIG_WRITE_WORD(MCCR1, mccr1);
  85        CONFIG_WRITE_WORD(MSAR1, msar1);
  86        CONFIG_WRITE_WORD(EMSAR1, emsar1);
  87        CONFIG_WRITE_WORD(MEAR1, mear1);
  88        CONFIG_WRITE_WORD(EMEAR1, emear1);
  89        CONFIG_WRITE_WORD(MSAR2, msar2);
  90        CONFIG_WRITE_WORD(EMSAR2, emsar2);
  91        CONFIG_WRITE_WORD(MEAR2, mear2);
  92        CONFIG_WRITE_WORD(EMEAR2, emear2);
  93        CONFIG_WRITE_BYTE(MBER, mber);
  94
  95        return (1 << (col + row + 3) ) * bank * m;
  96}
  97
  98phys_size_t initdram(int board_type)
  99{
 100        unsigned int msr;
 101        long int size = 0;
 102
 103        msr = mfmsr();
 104        mtmsr(msr & ~(MSR_IR | MSR_DR));
 105        mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
 106        mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
 107        mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
 108        mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
 109        mtmsr(msr);
 110
 111        if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
 112                size = 0x20000000;      /* 512MB */
 113        else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
 114                size = 0x10000000;      /* 256MB */
 115        else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
 116                size = 0x10000000;      /* 256MB */
 117        else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
 118                size = 0x08000000;      /* 128MB */
 119        else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
 120                size = 0x08000000;      /* 128MB */
 121        else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
 122                size = 0x04000000;      /* 64MB */
 123
 124        msr = mfmsr();
 125        mtmsr(msr & ~(MSR_IR | MSR_DR));
 126        mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
 127        mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
 128        mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
 129        mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
 130        mtmsr(msr);
 131
 132        return size;
 133}
 134
 135struct pci_controller hose;
 136
 137void pci_init_board(void)
 138{
 139        pci_mpc824x_init(&hose);
 140}
 141
 142int board_early_init_f(void)
 143{
 144        *(volatile unsigned char *)(0xff080120) = 0xfb;
 145
 146        return 0;
 147}
 148
 149int board_early_init_r(void)
 150{
 151        unsigned int msr;
 152
 153        CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
 154        CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
 155        CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
 156
 157        msr = mfmsr();
 158        mtmsr(msr & ~(MSR_IR | MSR_DR));
 159        mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
 160        mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
 161        mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
 162        mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
 163        mtmsr(msr);
 164
 165        return 0;
 166}
 167
 168extern int multiverse_init(void);
 169
 170int misc_init_r(void)
 171{
 172        multiverse_init();
 173        return 0;
 174}
 175
 176void *nvram_read(void *dest, const long src, size_t count)
 177{
 178        volatile uchar *d = (volatile uchar*) dest;
 179        volatile uchar *s = (volatile uchar*) src;
 180        while(count--) {
 181                *d++ = *s++;
 182                asm volatile("sync");
 183        }
 184        return dest;
 185}
 186
 187void nvram_write(long dest, const void *src, size_t count)
 188{
 189        volatile uchar *d = (volatile uchar*)dest;
 190        volatile uchar *s = (volatile uchar*)src;
 191        while(count--) {
 192                *d++ = *s++;
 193                asm volatile("sync");
 194        }
 195}
 196
 197int board_eth_init(bd_t *bis)
 198{
 199        return pci_eth_init(bis);
 200}
 201