LXR uboot/board/mcc200/mcc200.c

   1/*
   2 * (C) Copyright 2003-2006
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2004
   6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <mpc5xxx.h>
  29#include <pci.h>
  30#include <asm/processor.h>
  31
  32/* Two MT48LC8M32B2 for 32 MB */
  33/* #include "mt48lc8m32b2-6-7.h" */
  34
  35/* One MT48LC16M32S2 for 64 MB */
  36/* #include "mt48lc16m32s2-75.h" */
  37#if defined (CONFIG_MCC200_SDRAM)
  38#include "mt48lc16m16a2-75.h"
  39#else
  40#include "mt46v16m16-75.h"
  41#endif
  42
  43DECLARE_GLOBAL_DATA_PTR;
  44
  45extern flash_info_t flash_info[];       /* FLASH chips info */
  46
  47extern int do_auto_update(void);
  48ulong flash_get_size (ulong base, int banknum);
  49
  50#ifndef CONFIG_SYS_RAMBOOT
  51static void sdram_start (int hi_addr)
  52{
  53        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  54
  55        /* unlock mode register */
  56        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  57        __asm__ volatile ("sync");
  58
  59        /* precharge all banks */
  60        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  61        __asm__ volatile ("sync");
  62
  63#if SDRAM_DDR
  64        /* set mode register: extended mode */
  65        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  66        __asm__ volatile ("sync");
  67
  68        /* set mode register: reset DLL */
  69        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  70        __asm__ volatile ("sync");
  71#endif
  72
  73        /* precharge all banks */
  74        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  75        __asm__ volatile ("sync");
  76
  77        /* auto refresh */
  78        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  79        __asm__ volatile ("sync");
  80
  81        /* set mode register */
  82        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  83        __asm__ volatile ("sync");
  84
  85        /* normal operation */
  86        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  87        __asm__ volatile ("sync");
  88
  89        udelay(10);
  90}
  91#endif
  92
  93/*
  94 * ATTENTION: Although partially referenced initdram does NOT make real use
  95 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  96 *            is something else than 0x00000000.
  97 */
  98
  99phys_size_t initdram (int board_type)
 100{
 101        ulong dramsize = 0;
 102        ulong dramsize2 = 0;
 103        uint svr, pvr;
 104#ifndef CONFIG_SYS_RAMBOOT
 105        ulong test1, test2;
 106
 107        /* setup SDRAM chip selects */
 108        *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 109        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
 110        __asm__ volatile ("sync");
 111
 112        /* setup config registers */
 113        *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 114        *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 115        __asm__ volatile ("sync");
 116
 117#if SDRAM_DDR
 118        /* set tap delay */
 119        *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 120        __asm__ volatile ("sync");
 121#endif
 122
 123        /* find RAM size using SDRAM CS0 only */
 124        sdram_start(0);
 125        test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 126        sdram_start(1);
 127        test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 128        if (test1 > test2) {
 129                sdram_start(0);
 130                dramsize = test1;
 131        } else {
 132                dramsize = test2;
 133        }
 134
 135        /* memory smaller than 1MB is impossible */
 136        if (dramsize < (1 << 20)) {
 137                dramsize = 0;
 138        }
 139
 140        /* set SDRAM CS0 size according to the amount of RAM found */
 141        if (dramsize > 0) {
 142                *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 143        } else {
 144                *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 145        }
 146
 147        /* let SDRAM CS1 start right after CS0 */
 148        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 149
 150        /* find RAM size using SDRAM CS1 only */
 151        if (!dramsize)
 152                sdram_start(0);
 153        test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 154        if (!dramsize) {
 155                sdram_start(1);
 156                test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 157        }
 158        if (test1 > test2) {
 159                sdram_start(0);
 160                dramsize2 = test1;
 161        } else {
 162                dramsize2 = test2;
 163        }
 164
 165        /* memory smaller than 1MB is impossible */
 166        if (dramsize2 < (1 << 20)) {
 167                dramsize2 = 0;
 168        }
 169
 170        /* set SDRAM CS1 size according to the amount of RAM found */
 171        if (dramsize2 > 0) {
 172                *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 173                        | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 174        } else {
 175                *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 176        }
 177
 178#else /* CONFIG_SYS_RAMBOOT */
 179
 180        /* retrieve size of memory connected to SDRAM CS0 */
 181        dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 182        if (dramsize >= 0x13) {
 183                dramsize = (1 << (dramsize - 0x13)) << 20;
 184        } else {
 185                dramsize = 0;
 186        }
 187
 188        /* retrieve size of memory connected to SDRAM CS1 */
 189        dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 190        if (dramsize2 >= 0x13) {
 191                dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 192        } else {
 193                dramsize2 = 0;
 194        }
 195
 196#endif /* CONFIG_SYS_RAMBOOT */
 197
 198        /*
 199         * On MPC5200B we need to set the special configuration delay in the
 200         * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 201         * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 202         *
 203         * "The SDelay should be written to a value of 0x00000004. It is
 204         * required to account for changes caused by normal wafer processing
 205         * parameters."
 206         */
 207        svr = get_svr();
 208        pvr = get_pvr();
 209        if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 210                *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 211                __asm__ volatile ("sync");
 212        }
 213
 214        return dramsize + dramsize2;
 215}
 216
 217int checkboard (void)
 218{
 219#if defined(CONFIG_PRS200)
 220        puts ("Board: PRS200\n");
 221#else
 222        puts ("Board: MCC200\n");
 223#endif
 224        return 0;
 225}
 226
 227int misc_init_r (void)
 228{
 229        ulong flash_sup_end, snum;
 230
 231        /*
 232         * Adjust flash start and offset to detected values
 233         */
 234        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 235        gd->bd->bi_flashoffset = 0;
 236
 237        /*
 238         * Check if boot FLASH isn't max size
 239         */
 240        if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
 241                /* adjust mapping */
 242                *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 243                        START_REG(gd->bd->bi_flashstart);
 244                *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 245                        STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
 246
 247                /*
 248                 * Re-check to get correct base address
 249                 */
 250                flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
 251
 252                /*
 253                 * Re-do flash protection upon new addresses
 254                 */
 255                flash_protect (FLAG_PROTECT_CLEAR,
 256                               gd->bd->bi_flashstart, 0xffffffff,
 257                               &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 258
 259                /* Monitor protection ON by default */
 260                flash_protect (FLAG_PROTECT_SET,
 261                               CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 262                               &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 263
 264                /* Environment protection ON by default */
 265                flash_protect (FLAG_PROTECT_SET,
 266                               CONFIG_ENV_ADDR,
 267                               CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
 268                               &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 269
 270                /* Redundant environment protection ON by default */
 271                flash_protect (FLAG_PROTECT_SET,
 272                               CONFIG_ENV_ADDR_REDUND,
 273                               CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
 274                               &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 275        }
 276
 277        if (gd->bd->bi_flashsize > (32 << 20)) {
 278                /* Unprotect the upper bank of the Flash */
 279                *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
 280                flash_protect (FLAG_PROTECT_CLEAR,
 281                               flash_info[0].start[0] + flash_info[0].size / 2,
 282                               (flash_info[0].start[0] - 1) + flash_info[0].size,
 283                               &flash_info[0]);
 284                *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
 285                printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
 286                flash_info[0].size = 32 << 20;
 287                for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
 288                        flash_info[0].start[snum] < flash_sup_end;
 289                        snum++);
 290                flash_info[0].sector_count = snum;
 291        }
 292
 293#ifdef CONFIG_AUTO_UPDATE
 294        do_auto_update();
 295#endif
 296        return (0);
 297}
 298
 299#ifdef  CONFIG_PCI
 300static struct pci_controller hose;
 301
 302extern void pci_mpc5xxx_init(struct pci_controller *);
 303
 304void pci_init_board(void)
 305{
 306        pci_mpc5xxx_init(&hose);
 307}
 308#endif
 309
 310#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 311
 312void init_ide_reset (void)
 313{
 314        debug ("init_ide_reset\n");
 315
 316}
 317
 318void ide_set_reset (int idereset)
 319{
 320        debug ("ide_reset(%d)\n", idereset);
 321
 322}
 323#endif
 324
 325#if defined(CONFIG_CMD_DOC)
 326void doc_init (void)
 327{
 328        doc_probe (CONFIG_SYS_DOC_BASE);
 329}
 330#endif
 331