LXR uboot/board/sbc8548/sbc8548.c

   1/*
   2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
   3 *
   4 * Copyright 2007 Embedded Specialties, Inc.
   5 *
   6 * Copyright 2004, 2007 Freescale Semiconductor.
   7 *
   8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29#include <common.h>
  30#include <pci.h>
  31#include <asm/processor.h>
  32#include <asm/immap_85xx.h>
  33#include <asm/fsl_pci.h>
  34#include <asm/fsl_ddr_sdram.h>
  35#include <asm/fsl_serdes.h>
  36#include <spd_sdram.h>
  37#include <netdev.h>
  38#include <tsec.h>
  39#include <miiphy.h>
  40#include <libfdt.h>
  41#include <fdt_support.h>
  42
  43DECLARE_GLOBAL_DATA_PTR;
  44
  45void local_bus_init(void);
  46
  47int board_early_init_f (void)
  48{
  49        return 0;
  50}
  51
  52int checkboard (void)
  53{
  54        volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  55        volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
  56
  57        printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  58                        in_8(rev) >> 4);
  59
  60        /*
  61         * Initialize local bus.
  62         */
  63        local_bus_init ();
  64
  65        out_be32(&ecm->eedr, 0xffffffff);       /* clear ecm errors */
  66        out_be32(&ecm->eeer, 0xffffffff);       /* enable ecm errors */
  67        return 0;
  68}
  69
  70/*
  71 * Initialize Local Bus
  72 */
  73void
  74local_bus_init(void)
  75{
  76        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  77        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  78
  79        uint clkdiv;
  80        uint lbc_hz;
  81        sys_info_t sysinfo;
  82
  83        get_sys_info(&sysinfo);
  84        clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
  85        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
  86
  87        out_be32(&gur->lbiuiplldcr1, 0x00078080);
  88        if (clkdiv == 16) {
  89                out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  90        } else if (clkdiv == 8) {
  91                out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  92        } else if (clkdiv == 4) {
  93                out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  94        }
  95
  96        setbits_be32(&lbc->lcrr, 0x00030000);
  97
  98        asm("sync;isync;msync");
  99
 100        out_be32(&lbc->ltesr, 0xffffffff);      /* Clear LBC error IRQs */
 101        out_be32(&lbc->lteir, 0xffffffff);      /* Enable LBC error IRQs */
 102}
 103
 104/*
 105 * Initialize SDRAM memory on the Local Bus.
 106 */
 107void lbc_sdram_init(void)
 108{
 109#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 110
 111        uint idx;
 112        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 113        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 114        uint lsdmr_common;
 115
 116        puts("    SDRAM: ");
 117
 118        print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 119
 120        /*
 121         * Setup SDRAM Base and Option Registers
 122         */
 123        set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 124        set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 125        set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
 126        set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
 127
 128        out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 129        asm("msync");
 130
 131        out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
 132        out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 133        asm("msync");
 134
 135        /*
 136         * MPC8548 uses "new" 15-16 style addressing.
 137         */
 138        lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 139        lsdmr_common |= LSDMR_BSMA1516;
 140
 141        /*
 142         * Issue PRECHARGE ALL command.
 143         */
 144        out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
 145        asm("sync;msync");
 146        *sdram_addr = 0xff;
 147        ppcDcbf((unsigned long) sdram_addr);
 148        udelay(100);
 149
 150        /*
 151         * Issue 8 AUTO REFRESH commands.
 152         */
 153        for (idx = 0; idx < 8; idx++) {
 154                out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
 155                asm("sync;msync");
 156                *sdram_addr = 0xff;
 157                ppcDcbf((unsigned long) sdram_addr);
 158                udelay(100);
 159        }
 160
 161        /*
 162         * Issue 8 MODE-set command.
 163         */
 164        out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
 165        asm("sync;msync");
 166        *sdram_addr = 0xff;
 167        ppcDcbf((unsigned long) sdram_addr);
 168        udelay(100);
 169
 170        /*
 171         * Issue NORMAL OP command.
 172         */
 173        out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
 174        asm("sync;msync");
 175        *sdram_addr = 0xff;
 176        ppcDcbf((unsigned long) sdram_addr);
 177        udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 178
 179#endif  /* enable SDRAM init */
 180}
 181
 182#if defined(CONFIG_SYS_DRAM_TEST)
 183int
 184testdram(void)
 185{
 186        uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 187        uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 188        uint *p;
 189
 190        printf("Testing DRAM from 0x%08x to 0x%08x\n",
 191               CONFIG_SYS_MEMTEST_START,
 192               CONFIG_SYS_MEMTEST_END);
 193
 194        printf("DRAM test phase 1:\n");
 195        for (p = pstart; p < pend; p++)
 196                *p = 0xaaaaaaaa;
 197
 198        for (p = pstart; p < pend; p++) {
 199                if (*p != 0xaaaaaaaa) {
 200                        printf ("DRAM test fails at: %08x\n", (uint) p);
 201                        return 1;
 202                }
 203        }
 204
 205        printf("DRAM test phase 2:\n");
 206        for (p = pstart; p < pend; p++)
 207                *p = 0x55555555;
 208
 209        for (p = pstart; p < pend; p++) {
 210                if (*p != 0x55555555) {
 211                        printf ("DRAM test fails at: %08x\n", (uint) p);
 212                        return 1;
 213                }
 214        }
 215
 216        printf("DRAM test passed.\n");
 217        return 0;
 218}
 219#endif
 220
 221#if !defined(CONFIG_SPD_EEPROM)
 222#define CONFIG_SYS_DDR_CONTROL 0xc300c000
 223/*************************************************************************
 224 *  fixed_sdram init -- doesn't use serial presence detect.
 225 *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
 226 ************************************************************************/
 227phys_size_t fixed_sdram(void)
 228{
 229        volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 230
 231        out_be32(&ddr->cs0_bnds, 0x0000007f);
 232        out_be32(&ddr->cs1_bnds, 0x008000ff);
 233        out_be32(&ddr->cs2_bnds, 0x00000000);
 234        out_be32(&ddr->cs3_bnds, 0x00000000);
 235        out_be32(&ddr->cs0_config, 0x80010101);
 236        out_be32(&ddr->cs1_config, 0x80010101);
 237        out_be32(&ddr->cs2_config, 0x00000000);
 238        out_be32(&ddr->cs3_config, 0x00000000);
 239        out_be32(&ddr->timing_cfg_3, 0x00000000);
 240        out_be32(&ddr->timing_cfg_0, 0x00220802);
 241        out_be32(&ddr->timing_cfg_1, 0x38377322);
 242        out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
 243        out_be32(&ddr->sdram_cfg, 0x4300C000);
 244        out_be32(&ddr->sdram_cfg_2, 0x24401000);
 245        out_be32(&ddr->sdram_mode, 0x23C00542);
 246        out_be32(&ddr->sdram_mode_2, 0x00000000);
 247        out_be32(&ddr->sdram_interval, 0x05080100);
 248        out_be32(&ddr->sdram_md_cntl, 0x00000000);
 249        out_be32(&ddr->sdram_data_init, 0x00000000);
 250        out_be32(&ddr->sdram_clk_cntl, 0x03800000);
 251        asm("sync;isync;msync");
 252        udelay(500);
 253
 254        #if defined (CONFIG_DDR_ECC)
 255          /* Enable ECC checking */
 256          out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
 257        #else
 258          out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
 259        #endif
 260
 261        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 262}
 263#endif
 264
 265#ifdef CONFIG_PCI1
 266static struct pci_controller pci1_hose;
 267#endif  /* CONFIG_PCI1 */
 268
 269#ifdef CONFIG_PCI
 270void
 271pci_init_board(void)
 272{
 273        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 274        int first_free_busno = 0;
 275
 276#ifdef CONFIG_PCI1
 277        struct fsl_pci_info pci_info;
 278        u32 devdisr = in_be32(&gur->devdisr);
 279        u32 pordevsr = in_be32(&gur->pordevsr);
 280        u32 porpllsr = in_be32(&gur->porpllsr);
 281
 282        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 283                uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
 284                uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 285                uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 286                uint pci_speed = CONFIG_SYS_CLK_FREQ;   /* get_clock_freq() */
 287
 288                printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
 289                        (pci_32) ? 32 : 64,
 290                        (pci_speed == 33000000) ? "33" :
 291                        (pci_speed == 66000000) ? "66" : "unknown",
 292                        pci_clk_sel ? "sync" : "async",
 293                        pci_arb ? "arbiter" : "external-arbiter");
 294
 295                SET_STD_PCI_INFO(pci_info, 1);
 296                set_next_law(pci_info.mem_phys,
 297                        law_size_bits(pci_info.mem_size), pci_info.law);
 298                set_next_law(pci_info.io_phys,
 299                        law_size_bits(pci_info.io_size), pci_info.law);
 300
 301                first_free_busno = fsl_pci_init_port(&pci_info,
 302                                        &pci1_hose, first_free_busno);
 303        } else {
 304                printf("PCI: disabled\n");
 305        }
 306
 307        puts("\n");
 308#else
 309        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 310#endif
 311
 312        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 313
 314        fsl_pcie_init_board(first_free_busno);
 315}
 316#endif
 317
 318int board_eth_init(bd_t *bis)
 319{
 320        tsec_standard_init(bis);
 321        pci_eth_init(bis);
 322        return 0;       /* otherwise cpu_eth_init gets run */
 323}
 324
 325int last_stage_init(void)
 326{
 327        return 0;
 328}
 329
 330#if defined(CONFIG_OF_BOARD_SETUP)
 331void ft_board_setup(void *blob, bd_t *bd)
 332{
 333        ft_cpu_setup(blob, bd);
 334
 335#ifdef CONFIG_FSL_PCI_INIT
 336        FT_FSL_PCI_SETUP;
 337#endif
 338}
 339#endif
 340