uboot/board/timll/devkit8000/devkit8000.h
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   1/*
   2 * (C) Copyright 2008
   3 * Dirk Behme <dirk.behme@gmail.com>
   4 *
   5 * (C) Copyright 2009
   6 * Frederik Kriewitz <frederik@kriewitz.eu>
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26#ifndef _DEVKIT8000_H_
  27#define _DEVKIT8000_H_
  28
  29const omap3_sysinfo sysinfo = {
  30        DDR_STACKED,
  31        "OMAP3 DevKit8000",
  32        "NAND",
  33};
  34
  35/*
  36 * IEN  - Input Enable
  37 * IDIS - Input Disable
  38 * PTD  - Pull type Down
  39 * PTU  - Pull type Up
  40 * DIS  - Pull type selection is inactive
  41 * EN   - Pull type selection is active
  42 * M0   - Mode 0
  43 * The commented string gives the final mux configuration for that pin
  44 */
  45
  46#define MUX_DEVKIT8000() \
  47 /* SDRC */\
  48        MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
  49        MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
  50        MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
  51        MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
  52        MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
  53        MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
  54        MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
  55        MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
  56        MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
  57        MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
  58        MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
  59        MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
  60        MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
  61        MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
  62        MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
  63        MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
  64        MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
  65        MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
  66        MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
  67        MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
  68        MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
  69        MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
  70        MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
  71        MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
  72        MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
  73        MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
  74        MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
  75        MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
  76        MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
  77        MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
  78        MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
  79        MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
  80        MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
  81        MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
  82        MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
  83        MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
  84        MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
  85 /* GPMC */\
  86        MUX_VAL(CP(GPMC_A1),            (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
  87        MUX_VAL(CP(GPMC_A2),            (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
  88        MUX_VAL(CP(GPMC_A3),            (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
  89        MUX_VAL(CP(GPMC_A4),            (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
  90        MUX_VAL(CP(GPMC_A5),            (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
  91        MUX_VAL(CP(GPMC_A6),            (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
  92        MUX_VAL(CP(GPMC_A7),            (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
  93        MUX_VAL(CP(GPMC_A8),            (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
  94        MUX_VAL(CP(GPMC_A9),            (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
  95        MUX_VAL(CP(GPMC_A10),           (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
  96        MUX_VAL(CP(GPMC_D0),            (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
  97        MUX_VAL(CP(GPMC_D1),            (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
  98        MUX_VAL(CP(GPMC_D2),            (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
  99        MUX_VAL(CP(GPMC_D3),            (IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
 100        MUX_VAL(CP(GPMC_D4),            (IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
 101        MUX_VAL(CP(GPMC_D5),            (IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
 102        MUX_VAL(CP(GPMC_D6),            (IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
 103        MUX_VAL(CP(GPMC_D7),            (IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
 104        MUX_VAL(CP(GPMC_D8),            (IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
 105        MUX_VAL(CP(GPMC_D9),            (IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
 106        MUX_VAL(CP(GPMC_D10),           (IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
 107        MUX_VAL(CP(GPMC_D11),           (IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
 108        MUX_VAL(CP(GPMC_D12),           (IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
 109        MUX_VAL(CP(GPMC_D13),           (IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
 110        MUX_VAL(CP(GPMC_D14),           (IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
 111        MUX_VAL(CP(GPMC_D15),           (IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
 112        MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS0 NAND*/\
 113        MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
 114        MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
 115        MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
 116        MUX_VAL(CP(GPMC_NCS4),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
 117        MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
 118        MUX_VAL(CP(GPMC_NCS6),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS6 DM9000*/\
 119        MUX_VAL(CP(GPMC_NCS7),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
 120        MUX_VAL(CP(GPMC_NBE1),          (IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
 121        MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
 122        MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
 123        MUX_VAL(CP(GPMC_CLK),           (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
 124        MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 125        MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 126        MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 127        MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
 128        MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 129        MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 130        MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
 131 /* DSS */\
 132        MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 133        MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
 134        MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
 135        MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
 136        MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
 137        MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
 138        MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
 139        MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
 140        MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
 141        MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
 142        MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
 143        MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
 144        MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
 145        MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
 146        MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
 147        MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
 148        MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
 149        MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
 150        MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
 151        MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
 152        MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
 153        MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
 154        MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
 155        MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
 156        MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
 157        MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
 158        MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
 159        MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
 160 /* CAMERA */\
 161        MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) /*CAM_HS */\
 162        MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) /*CAM_VS */\
 163        MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 164        MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
 165        MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
 166        MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 167        MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 168        MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
 169        MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
 170        MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
 171        MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
 172        MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
 173        MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
 174        MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
 175        MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 176        MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 177        MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
 178        MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 179        MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 180        MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 181        MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
 182        MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
 183        MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
 184        MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
 185 /* Audio Interface */\
 186        MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 187        MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 188        MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 189        MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
 190 /* MMC Slot */\
 191        MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
 192        MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 193        MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 194        MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
 195        MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
 196        MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
 197        MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
 198        MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
 199        MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 200        MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
 201 /* Expansion Header */\
 202        MUX_VAL(CP(MMC2_CLK),           (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 203        MUX_VAL(CP(MMC2_CMD),           (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
 204        MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
 205        MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
 206        MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
 207        MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
 208        MUX_VAL(CP(MMC2_DAT4),          (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
 209        MUX_VAL(CP(MMC2_DAT5),          (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
 210        MUX_VAL(CP(MMC2_DAT6),          (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
 211        MUX_VAL(CP(MMC2_DAT7),          (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
 212        MUX_VAL(CP(MCBSP3_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
 213        MUX_VAL(CP(MCBSP3_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
 214        MUX_VAL(CP(MCBSP3_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
 215        MUX_VAL(CP(MCBSP3_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
 216        MUX_VAL(CP(UART2_CTS),          (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
 217        MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
 218        MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
 219        MUX_VAL(CP(UART2_RX),           (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
 220        MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
 221        MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
 222        MUX_VAL(CP(UART1_CTS),          (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
 223        MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) /*GPIO_151*/\
 224        MUX_VAL(CP(MCBSP4_CLKX),        (IEN  | PTD | DIS | M1)) /*GPIO_152*/\
 225        MUX_VAL(CP(MCBSP4_DR),          (IEN  | PTD | DIS | M1)) /*GPIO_153*/\
 226        MUX_VAL(CP(MCBSP4_DX),          (IEN  | PTD | DIS | M1)) /*GPIO_154*/\
 227        MUX_VAL(CP(MCBSP4_FSX),         (IEN  | PTD | DIS | M1)) /*GPIO_155*/\
 228        MUX_VAL(CP(MCBSP1_CLKR),        (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
 229        MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M4)) /*GPIO_157*/\
 230        MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
 231        MUX_VAL(CP(MCBSP1_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
 232        MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) /*GPIO_160*/\
 233        MUX_VAL(CP(MCBSP1_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
 234        MUX_VAL(CP(MCBSP1_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
 235 /* Serial Interface */\
 236        MUX_VAL(CP(UART3_CTS_RCTX),     (IDIS | PTD | EN  | M4)) /*GPIO_163 - LED2*/\
 237        MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTU | EN  | M4)) /*GPIO_164 - LED3*/\
 238        MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
 239        MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 240 /* Host USB0 */\
 241        MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
 242        MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
 243        MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
 244        MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
 245        MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
 246        MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
 247        MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
 248        MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
 249        MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
 250        MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
 251        MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
 252        MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
 253        MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
 254        MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
 255        MUX_VAL(CP(I2C2_SCL),           (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
 256        MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
 257        MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
 258        MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 259        MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 260        MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | DIS | M0)) /*I2C4_SDA*/\
 261        MUX_VAL(CP(HDQ_SIO),            (IDIS | PTD | DIS | M4)) /*GPIO_170*/\
 262        MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTD | DIS | M4)) /*GPIO_171*/\
 263        MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTD | DIS | M4)) /*GPIO_172*/\
 264        MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
 265        MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | DIS | M0)) /*MCSPI1_CS0*/\
 266        MUX_VAL(CP(MCSPI1_CS1),         (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
 267        MUX_VAL(CP(MCSPI1_CS2),         (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
 268 /* USB EHCI (port 2) */\
 269        MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/\
 270        MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
 271        MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
 272        MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
 273        MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/\
 274        MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/\
 275 /*Control and debug */\
 276        MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 277        MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
 278        MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
 279        MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 280        MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
 281        MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
 282        MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
 283        MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
 284        MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 285        MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
 286        MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 287        MUX_VAL(CP(SYS_CLKOUT1),        (IDIS | PTD | EN  | M0)) /*SYS_CLKOUT1*/\
 288        MUX_VAL(CP(SYS_CLKOUT2),        (IDIS | PTU | EN  | M4)) /*GPIO_186 - LED1*/\
 289        MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
 290        MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | EN  | M3)) /*HSUSB1_CLK*/\
 291        MUX_VAL(CP(ETK_D0_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA0*/\
 292        MUX_VAL(CP(ETK_D1_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA1*/\
 293        MUX_VAL(CP(ETK_D2_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA2*/\
 294        MUX_VAL(CP(ETK_D3_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA7*/\
 295        MUX_VAL(CP(ETK_D4_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA4*/\
 296        MUX_VAL(CP(ETK_D5_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA5*/\
 297        MUX_VAL(CP(ETK_D6_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA6*/\
 298        MUX_VAL(CP(ETK_D7_ES2),         (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA3*/\
 299        MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTD | DIS | M3)) /*HSUSB1_DIR*/\
 300        MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTD | DIS | M3)) /*HSUSB1_NXT*/\
 301        MUX_VAL(CP(ETK_D10_ES2),        (IDIS | PTU | EN  | M4)) /*GPIO_24*/\
 302        MUX_VAL(CP(ETK_D11_ES2),        (IEN  | PTU | EN  | M4)) /*GPIO_25*/\
 303        MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTU | EN  | M4)) /*GPIO_26*/\
 304        MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTU | EN  | M4)) /*GPIO_27*/\
 305        MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTU | EN  | M4)) /*GPIO_28*/\
 306        MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTU | EN  | M4)) /*GPIO_29*/\
 307        MUX_VAL(CP(D2D_MCAD1),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD1*/\
 308        MUX_VAL(CP(D2D_MCAD2),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD2*/\
 309        MUX_VAL(CP(D2D_MCAD3),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD3*/\
 310        MUX_VAL(CP(D2D_MCAD4),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD4*/\
 311        MUX_VAL(CP(D2D_MCAD5),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD5*/\
 312        MUX_VAL(CP(D2D_MCAD6),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD6*/\
 313        MUX_VAL(CP(D2D_MCAD7),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD7*/\
 314        MUX_VAL(CP(D2D_MCAD8),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD8*/\
 315        MUX_VAL(CP(D2D_MCAD9),          (IEN  | PTD | EN  | M0)) /*D2D_MCAD9*/\
 316        MUX_VAL(CP(D2D_MCAD10),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD10*/\
 317        MUX_VAL(CP(D2D_MCAD11),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD11*/\
 318        MUX_VAL(CP(D2D_MCAD12),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD12*/\
 319        MUX_VAL(CP(D2D_MCAD13),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD13*/\
 320        MUX_VAL(CP(D2D_MCAD14),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD14*/\
 321        MUX_VAL(CP(D2D_MCAD15),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD15*/\
 322        MUX_VAL(CP(D2D_MCAD16),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD16*/\
 323        MUX_VAL(CP(D2D_MCAD17),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD17*/\
 324        MUX_VAL(CP(D2D_MCAD18),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD18*/\
 325        MUX_VAL(CP(D2D_MCAD19),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD19*/\
 326        MUX_VAL(CP(D2D_MCAD20),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD20*/\
 327        MUX_VAL(CP(D2D_MCAD21),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD21*/\
 328        MUX_VAL(CP(D2D_MCAD22),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD22*/\
 329        MUX_VAL(CP(D2D_MCAD23),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD23*/\
 330        MUX_VAL(CP(D2D_MCAD24),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD24*/\
 331        MUX_VAL(CP(D2D_MCAD25),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD25*/\
 332        MUX_VAL(CP(D2D_MCAD26),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD26*/\
 333        MUX_VAL(CP(D2D_MCAD27),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD27*/\
 334        MUX_VAL(CP(D2D_MCAD28),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD28*/\
 335        MUX_VAL(CP(D2D_MCAD29),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD29*/\
 336        MUX_VAL(CP(D2D_MCAD30),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD30*/\
 337        MUX_VAL(CP(D2D_MCAD31),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD31*/\
 338        MUX_VAL(CP(D2D_MCAD32),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD32*/\
 339        MUX_VAL(CP(D2D_MCAD33),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD33*/\
 340        MUX_VAL(CP(D2D_MCAD34),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD34*/\
 341        MUX_VAL(CP(D2D_MCAD35),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD35*/\
 342        MUX_VAL(CP(D2D_MCAD36),         (IEN  | PTD | EN  | M0)) /*D2D_MCAD36*/\
 343        MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0)) /*D2D_clk26mi*/\
 344        MUX_VAL(CP(D2D_NRESPWRON),      (IEN  | PTD | EN  | M0)) /*D2D_nrespwron*/\
 345        MUX_VAL(CP(D2D_NRESWARM),       (IEN  | PTU | EN  | M0)) /*D2D_nreswarm */\
 346        MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0)) /*D2D_arm9nirq */\
 347        MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
 348        MUX_VAL(CP(D2D_SPINT),          (IEN  | PTD | EN  | M0)) /*D2D_spint*/\
 349        MUX_VAL(CP(D2D_FRINT),          (IEN  | PTD | EN  | M0)) /*D2D_frint*/\
 350        MUX_VAL(CP(D2D_DMAREQ0),        (IEN  | PTD | DIS | M0)) /*D2D_dmareq0*/\
 351        MUX_VAL(CP(D2D_DMAREQ1),        (IEN  | PTD | DIS | M0)) /*D2D_dmareq1*/\
 352        MUX_VAL(CP(D2D_DMAREQ2),        (IEN  | PTD | DIS | M0)) /*D2D_dmareq2*/\
 353        MUX_VAL(CP(D2D_DMAREQ3),        (IEN  | PTD | DIS | M0)) /*D2D_dmareq3*/\
 354        MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0)) /*D2D_n3gtrst*/\
 355        MUX_VAL(CP(D2D_N3GTDI),         (IEN  | PTD | DIS | M0)) /*D2D_n3gtdi*/\
 356        MUX_VAL(CP(D2D_N3GTDO),         (IEN  | PTD | DIS | M0)) /*D2D_n3gtdo*/\
 357        MUX_VAL(CP(D2D_N3GTMS),         (IEN  | PTD | DIS | M0)) /*D2D_n3gtms*/\
 358        MUX_VAL(CP(D2D_N3GTCK),         (IEN  | PTD | DIS | M0)) /*D2D_n3gtck*/\
 359        MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0)) /*D2D_n3grtck*/\
 360        MUX_VAL(CP(D2D_MSTDBY),         (IEN  | PTU | EN  | M0)) /*D2D_mstdby*/\
 361        MUX_VAL(CP(D2D_SWAKEUP),        (IEN  | PTD | EN  | M0)) /*D2D_swakeup*/\
 362        MUX_VAL(CP(D2D_IDLEREQ),        (IEN  | PTD | DIS | M0)) /*D2D_idlereq*/\
 363        MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0)) /*D2D_idleack*/\
 364        MUX_VAL(CP(D2D_MWRITE),         (IEN  | PTD | DIS | M0)) /*D2D_mwrite*/\
 365        MUX_VAL(CP(D2D_SWRITE),         (IEN  | PTD | DIS | M0)) /*D2D_swrite*/\
 366        MUX_VAL(CP(D2D_MREAD),          (IEN  | PTD | DIS | M0)) /*D2D_mread*/\
 367        MUX_VAL(CP(D2D_SREAD),          (IEN  | PTD | DIS | M0)) /*D2D_sread*/\
 368        MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0)) /*D2D_mbusflag*/\
 369        MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0)) /*D2D_sbusflag*/\
 370        MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 371        MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
 372
 373#endif
 374
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.