LXR uboot/board/tqc/tqm8xx/tqm8xx.c

   1/*
   2 * (C) Copyright 2000-2008
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <hwconfig.h>
  26#include <mpc8xx.h>
  27#ifdef CONFIG_PS2MULT
  28#include <ps2mult.h>
  29#endif
  30
  31#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  32#include <libfdt.h>
  33#endif
  34
  35extern flash_info_t flash_info[];       /* FLASH chips info */
  36
  37DECLARE_GLOBAL_DATA_PTR;
  38
  39static long int dram_size (long int, long int *, long int);
  40
  41#define _NOT_USED_      0xFFFFFFFF
  42
  43/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
  44const uint sdram_table[] =
  45{
  46        /*
  47         * Single Read. (Offset 0 in UPMA RAM)
  48         */
  49        0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
  50        0x1FF5FC47, /* last */
  51        /*
  52         * SDRAM Initialization (offset 5 in UPMA RAM)
  53         *
  54         * This is no UPM entry point. The following definition uses
  55         * the remaining space to establish an initialization
  56         * sequence, which is executed by a RUN command.
  57         *
  58         */
  59                    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
  60        /*
  61         * Burst Read. (Offset 8 in UPMA RAM)
  62         */
  63        0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
  64        0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
  65        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  67        /*
  68         * Single Write. (Offset 18 in UPMA RAM)
  69         */
  70        0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
  71        0x1FF5FC47, /* last */
  72                    _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73        /*
  74         * Burst Write. (Offset 20 in UPMA RAM)
  75         */
  76        0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  77        0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
  78        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  79        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  80        /*
  81         * Refresh  (Offset 30 in UPMA RAM)
  82         */
  83        0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  84        0xFFFFFC84, 0xFFFFFC07, /* last */
  85                                _NOT_USED_, _NOT_USED_,
  86        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  87        /*
  88         * Exception. (Offset 3c in UPMA RAM)
  89         */
  90        0xFFFFFC07, /* last */
  91                    _NOT_USED_, _NOT_USED_, _NOT_USED_,
  92};
  93
  94/* ------------------------------------------------------------------------- */
  95
  96
  97/*
  98 * Check Board Identity:
  99 *
 100 * Test TQ ID string (TQM8xx...)
 101 * If present, check for "L" type (no second DRAM bank),
 102 * otherwise "L" type is assumed as default.
 103 *
 104 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
 105 */
 106
 107int checkboard (void)
 108{
 109        char buf[64];
 110        int i;
 111        int l = getenv_f("serial#", buf, sizeof(buf));
 112
 113        puts ("Board: ");
 114
 115        if (l < 0 || strncmp(buf, "TQM8", 4)) {
 116                puts ("### No HW ID - assuming TQM8xxL\n");
 117                return (0);
 118        }
 119
 120        if ((buf[6] == 'L')) {  /* a TQM8xxL type */
 121                gd->board_type = 'L';
 122        }
 123
 124        if ((buf[6] == 'M')) {  /* a TQM8xxM type */
 125                gd->board_type = 'M';
 126        }
 127
 128        if ((buf[6] == 'D')) {  /* a TQM885D type */
 129                gd->board_type = 'D';
 130        }
 131
 132        for (i = 0; i < l; ++i) {
 133                if (buf[i] == ' ')
 134                        break;
 135                putc (buf[i]);
 136        }
 137#ifdef CONFIG_VIRTLAB2
 138        puts (" (Virtlab2)");
 139#endif
 140        putc ('\n');
 141
 142        return (0);
 143}
 144
 145/* ------------------------------------------------------------------------- */
 146
 147phys_size_t initdram (int board_type)
 148{
 149        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 150        volatile memctl8xx_t *memctl = &immap->im_memctl;
 151        long int size8, size9, size10;
 152        long int size_b0 = 0;
 153        long int size_b1 = 0;
 154
 155        upmconfig (UPMA, (uint *) sdram_table,
 156                           sizeof (sdram_table) / sizeof (uint));
 157
 158        /*
 159         * Preliminary prescaler for refresh (depends on number of
 160         * banks): This value is selected for four cycles every 62.4 us
 161         * with two SDRAM banks or four cycles every 31.2 us with one
 162         * bank. It will be adjusted after memory sizing.
 163         */
 164        memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 165
 166        /*
 167         * The following value is used as an address (i.e. opcode) for
 168         * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
 169         * the port size is 32bit the SDRAM does NOT "see" the lower two
 170         * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
 171         * MICRON SDRAMs:
 172         * ->    0 00 010 0 010
 173         *       |  |   | |   +- Burst Length = 4
 174         *       |  |   | +----- Burst Type   = Sequential
 175         *       |  |   +------- CAS Latency  = 2
 176         *       |  +----------- Operating Mode = Standard
 177         *       +-------------- Write Burst Mode = Programmed Burst Length
 178         */
 179        memctl->memc_mar = 0x00000088;
 180
 181        /*
 182         * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 183         * preliminary addresses - these have to be modified after the
 184         * SDRAM size has been determined.
 185         */
 186        memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 187        memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 188
 189#ifndef CONFIG_CAN_DRIVER
 190        if ((board_type != 'L') &&
 191            (board_type != 'M') &&
 192            (board_type != 'D') ) {     /* only one SDRAM bank on L, M and D modules */
 193                memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 194                memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 195        }
 196#endif                                                  /* CONFIG_CAN_DRIVER */
 197
 198        memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 199
 200        udelay (200);
 201
 202        /* perform SDRAM initializsation sequence */
 203
 204        memctl->memc_mcr = 0x80004105;  /* SDRAM bank 0 */
 205        udelay (1);
 206        memctl->memc_mcr = 0x80004230;  /* SDRAM bank 0 - execute twice */
 207        udelay (1);
 208
 209#ifndef CONFIG_CAN_DRIVER
 210        if ((board_type != 'L') &&
 211            (board_type != 'M') &&
 212            (board_type != 'D') ) {     /* only one SDRAM bank on L, M and D modules */
 213                memctl->memc_mcr = 0x80006105;  /* SDRAM bank 1 */
 214                udelay (1);
 215                memctl->memc_mcr = 0x80006230;  /* SDRAM bank 1 - execute twice */
 216                udelay (1);
 217        }
 218#endif                                                  /* CONFIG_CAN_DRIVER */
 219
 220        memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 221
 222        udelay (1000);
 223
 224        /*
 225         * Check Bank 0 Memory Size for re-configuration
 226         *
 227         * try 8 column mode
 228         */
 229        size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 230        debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
 231
 232        udelay (1000);
 233
 234        /*
 235         * try 9 column mode
 236         */
 237        size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 238        debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
 239
 240        udelay(1000);
 241
 242#if defined(CONFIG_SYS_MAMR_10COL)
 243        /*
 244         * try 10 column mode
 245         */
 246        size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 247        debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
 248#else
 249        size10 = 0;
 250#endif /* CONFIG_SYS_MAMR_10COL */
 251
 252        if ((size8 < size10) && (size9 < size10)) {
 253                size_b0 = size10;
 254        } else if ((size8 < size9) && (size10 < size9)) {
 255                size_b0 = size9;
 256                memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
 257                udelay (500);
 258        } else {
 259                size_b0 = size8;
 260                memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 261                udelay (500);
 262        }
 263        debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
 264
 265#ifndef CONFIG_CAN_DRIVER
 266        if ((board_type != 'L') &&
 267            (board_type != 'M') &&
 268            (board_type != 'D') ) {     /* only one SDRAM bank on L, M and D modules */
 269                /*
 270                 * Check Bank 1 Memory Size
 271                 * use current column settings
 272                 * [9 column SDRAM may also be used in 8 column mode,
 273                 *  but then only half the real size will be used.]
 274                 */
 275                size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
 276                                     SDRAM_MAX_SIZE);
 277                debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
 278        } else {
 279                size_b1 = 0;
 280        }
 281#endif  /* CONFIG_CAN_DRIVER */
 282
 283        udelay (1000);
 284
 285        /*
 286         * Adjust refresh rate depending on SDRAM type, both banks
 287         * For types > 128 MBit leave it at the current (fast) rate
 288         */
 289        if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 290                /* reduce to 15.6 us (62.4 us / quad) */
 291                memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 292                udelay (1000);
 293        }
 294
 295        /*
 296         * Final mapping: map bigger bank first
 297         */
 298        if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
 299
 300                memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 301                memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 302
 303                if (size_b0 > 0) {
 304                        /*
 305                         * Position Bank 0 immediately above Bank 1
 306                         */
 307                        memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 308                        memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 309                                           + size_b1;
 310                } else {
 311                        unsigned long reg;
 312
 313                        /*
 314                         * No bank 0
 315                         *
 316                         * invalidate bank
 317                         */
 318                        memctl->memc_br2 = 0;
 319
 320                        /* adjust refresh rate depending on SDRAM type, one bank */
 321                        reg = memctl->memc_mptpr;
 322                        reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 323                        memctl->memc_mptpr = reg;
 324                }
 325
 326        } else {                                        /* SDRAM Bank 0 is bigger - map first   */
 327
 328                memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 329                memctl->memc_br2 =
 330                                (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 331
 332                if (size_b1 > 0) {
 333                        /*
 334                         * Position Bank 1 immediately above Bank 0
 335                         */
 336                        memctl->memc_or3 =
 337                                        ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 338                        memctl->memc_br3 =
 339                                        ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 340                                        + size_b0;
 341                } else {
 342                        unsigned long reg;
 343
 344#ifndef CONFIG_CAN_DRIVER
 345                        /*
 346                         * No bank 1
 347                         *
 348                         * invalidate bank
 349                         */
 350                        memctl->memc_br3 = 0;
 351#endif                                                  /* CONFIG_CAN_DRIVER */
 352
 353                        /* adjust refresh rate depending on SDRAM type, one bank */
 354                        reg = memctl->memc_mptpr;
 355                        reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 356                        memctl->memc_mptpr = reg;
 357                }
 358        }
 359
 360        udelay (10000);
 361
 362#ifdef  CONFIG_CAN_DRIVER
 363        /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
 364
 365        /* Initialize OR3 / BR3 */
 366        memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
 367        memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 368
 369        /* Initialize MBMR */
 370        memctl->memc_mbmr = MBMR_GPL_B4DIS;     /* GPL_B4 ouput line Disable */
 371
 372        /* Initialize UPMB for CAN: single read */
 373        memctl->memc_mdr = 0xFFFFCC04;
 374        memctl->memc_mcr = 0x0100 | UPMB;
 375
 376        memctl->memc_mdr = 0x0FFFD004;
 377        memctl->memc_mcr = 0x0101 | UPMB;
 378
 379        memctl->memc_mdr = 0x0FFFC000;
 380        memctl->memc_mcr = 0x0102 | UPMB;
 381
 382        memctl->memc_mdr = 0x3FFFC004;
 383        memctl->memc_mcr = 0x0103 | UPMB;
 384
 385        memctl->memc_mdr = 0xFFFFDC07;
 386        memctl->memc_mcr = 0x0104 | UPMB;
 387
 388        /* Initialize UPMB for CAN: single write */
 389        memctl->memc_mdr = 0xFFFCCC04;
 390        memctl->memc_mcr = 0x0118 | UPMB;
 391
 392        memctl->memc_mdr = 0xCFFCDC04;
 393        memctl->memc_mcr = 0x0119 | UPMB;
 394
 395        memctl->memc_mdr = 0x3FFCC000;
 396        memctl->memc_mcr = 0x011A | UPMB;
 397
 398        memctl->memc_mdr = 0xFFFCC004;
 399        memctl->memc_mcr = 0x011B | UPMB;
 400
 401        memctl->memc_mdr = 0xFFFDC405;
 402        memctl->memc_mcr = 0x011C | UPMB;
 403#endif                                                  /* CONFIG_CAN_DRIVER */
 404
 405#ifdef  CONFIG_ISP1362_USB
 406        /* Initialize OR5 / BR5 */
 407        memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
 408        memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
 409#endif                                                  /* CONFIG_ISP1362_USB */
 410        return (size_b0 + size_b1);
 411}
 412
 413/* ------------------------------------------------------------------------- */
 414
 415/*
 416 * Check memory range for valid RAM. A simple memory test determines
 417 * the actually available RAM size between addresses `base' and
 418 * `base + maxsize'. Some (not all) hardware errors are detected:
 419 * - short between address lines
 420 * - short between data lines
 421 */
 422
 423static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 424{
 425        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 426        volatile memctl8xx_t *memctl = &immap->im_memctl;
 427
 428        memctl->memc_mamr = mamr_value;
 429
 430        return (get_ram_size(base, maxsize));
 431}
 432
 433/* ------------------------------------------------------------------------- */
 434
 435#ifdef CONFIG_MISC_INIT_R
 436extern void load_sernum_ethaddr(void);
 437int misc_init_r (void)
 438{
 439        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 440        volatile memctl8xx_t *memctl = &immap->im_memctl;
 441
 442        load_sernum_ethaddr();
 443
 444#ifdef  CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 445        int scy, trlx, flash_or_timing, clk_diff;
 446
 447        scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
 448        if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
 449                trlx = OR_TRLX;
 450                scy *= 2;
 451        } else {
 452                trlx = 0;
 453        }
 454
 455        /*
 456         * We assume that each 10MHz of bus clock require 1-clk SCY
 457         * adjustment.
 458         */
 459        clk_diff = (gd->bus_clk / 1000000) - 50;
 460
 461        /*
 462         * We need proper rounding here. This is what the "+5" and "-5"
 463         * are here for.
 464         */
 465        if (clk_diff >= 0)
 466                scy += (clk_diff + 5) / 10;
 467        else
 468                scy += (clk_diff - 5) / 10;
 469
 470        /*
 471         * For bus frequencies above 50MHz, we want to use relaxed timing
 472         * (OR_TRLX).
 473         */
 474        if (gd->bus_clk >= 50000000)
 475                trlx = OR_TRLX;
 476        else
 477                trlx = 0;
 478
 479        if (trlx)
 480                scy /= 2;
 481
 482        if (scy > 0xf)
 483                scy = 0xf;
 484        if (scy < 1)
 485                scy = 1;
 486
 487        flash_or_timing = (scy << 4) | trlx |
 488                (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
 489
 490        memctl->memc_or0 =
 491                flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
 492#else
 493        memctl->memc_or0 =
 494                CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
 495#endif
 496        memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 497
 498        debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
 499               memctl->memc_br0, memctl->memc_or0);
 500
 501        if (flash_info[1].size) {
 502#ifdef  CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 503                memctl->memc_or1 = flash_or_timing |
 504                        (-flash_info[1].size & 0xFFFF8000);
 505#else
 506                memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
 507                        (-flash_info[1].size & 0xFFFF8000);
 508#endif
 509                memctl->memc_br1 =
 510                        ((CONFIG_SYS_FLASH_BASE +
 511                          flash_info[0].
 512                          size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 513
 514                debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
 515                       memctl->memc_br1, memctl->memc_or1);
 516        } else {
 517                memctl->memc_br1 = 0;   /* invalidate bank */
 518
 519                debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
 520                       memctl->memc_br1, memctl->memc_or1);
 521        }
 522
 523# ifdef CONFIG_IDE_LED
 524        /* Configure PA15 as output port */
 525        immap->im_ioport.iop_padir |= 0x0001;
 526        immap->im_ioport.iop_paodr |= 0x0001;
 527        immap->im_ioport.iop_papar &= ~0x0001;
 528        immap->im_ioport.iop_padat &= ~0x0001;  /* turn it off */
 529# endif
 530
 531#ifdef CONFIG_NSCU
 532        /* wake up ethernet module */
 533        immap->im_ioport.iop_pcpar &= ~0x0004;  /* GPIO pin      */
 534        immap->im_ioport.iop_pcdir |= 0x0004;   /* output        */
 535        immap->im_ioport.iop_pcso &= ~0x0004;   /* for clarity   */
 536        immap->im_ioport.iop_pcdat |= 0x0004;   /* enable        */
 537#endif /* CONFIG_NSCU */
 538
 539        return (0);
 540}
 541#endif  /* CONFIG_MISC_INIT_R */
 542
 543
 544# ifdef CONFIG_IDE_LED
 545void ide_led (uchar led, uchar status)
 546{
 547        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 548
 549        /* We have one led for both pcmcia slots */
 550        if (status) {                           /* led on */
 551                immap->im_ioport.iop_padat |= 0x0001;
 552        } else {
 553                immap->im_ioport.iop_padat &= ~0x0001;
 554        }
 555}
 556# endif
 557
 558#ifdef CONFIG_LCD_INFO
 559#include <lcd.h>
 560#include <version.h>
 561#include <timestamp.h>
 562
 563void lcd_show_board_info(void)
 564{
 565        char temp[32];
 566
 567        lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
 568        lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
 569        lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
 570#ifdef CONFIG_LCD_INFO_BELOW_LOGO
 571        lcd_printf ("MPC823 CPU at %s MHz\n",
 572                strmhz(temp, gd->cpu_clk));
 573        lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
 574                gd->ram_size >> 20,
 575                gd->bd->bi_flashsize >> 20 );
 576#else
 577        /* leave one blank line */
 578        lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
 579                strmhz(temp, gd->cpu_clk),
 580                gd->ram_size >> 20,
 581                gd->bd->bi_flashsize >> 20 );
 582#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
 583}
 584#endif /* CONFIG_LCD_INFO */
 585
 586/*
 587 * Device Tree Support
 588 */
 589#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 590int fdt_set_node_and_value (void *blob,
 591                                char *nodename,
 592                                char *regname,
 593                                void *var,
 594                                int size)
 595{
 596        int ret = 0;
 597        int nodeoffset = 0;
 598
 599        nodeoffset = fdt_path_offset (blob, nodename);
 600        if (nodeoffset >= 0) {
 601                ret = fdt_setprop (blob, nodeoffset, regname, var,
 602                                        size);
 603                if (ret < 0) {
 604                        printf("ft_blob_update(): "
 605                                "cannot set %s/%s property; err: %s\n",
 606                                nodename, regname, fdt_strerror (ret));
 607                }
 608        } else {
 609                printf("ft_blob_update(): "
 610                        "cannot find %s node err:%s\n",
 611                        nodename, fdt_strerror (nodeoffset));
 612        }
 613        return ret;
 614}
 615
 616int fdt_del_node_name (void *blob, char *nodename)
 617{
 618        int ret = 0;
 619        int nodeoffset = 0;
 620
 621        nodeoffset = fdt_path_offset (blob, nodename);
 622        if (nodeoffset >= 0) {
 623                ret = fdt_del_node (blob, nodeoffset);
 624                if (ret < 0) {
 625                        printf("%s: cannot delete %s; err: %s\n",
 626                                __func__, nodename, fdt_strerror (ret));
 627                }
 628        } else {
 629                printf("%s: cannot find %s node err:%s\n",
 630                        __func__, nodename, fdt_strerror (nodeoffset));
 631        }
 632        return ret;
 633}
 634
 635int fdt_del_prop_name (void *blob, char *nodename, char *propname)
 636{
 637        int ret = 0;
 638        int nodeoffset = 0;
 639
 640        nodeoffset = fdt_path_offset (blob, nodename);
 641        if (nodeoffset >= 0) {
 642                ret = fdt_delprop (blob, nodeoffset, propname);
 643                if (ret < 0) {
 644                        printf("%s: cannot delete %s %s; err: %s\n",
 645                                __func__, nodename, propname,
 646                                fdt_strerror (ret));
 647                }
 648        } else {
 649                printf("%s: cannot find %s node err:%s\n",
 650                        __func__, nodename, fdt_strerror (nodeoffset));
 651        }
 652        return ret;
 653}
 654
 655/*
 656 * update "brg" property in the blob
 657 */
 658void ft_blob_update (void *blob, bd_t *bd)
 659{
 660        uchar enetaddr[6];
 661        ulong brg_data = 0;
 662
 663        /* BRG */
 664        brg_data = cpu_to_be32(bd->bi_busfreq);
 665        fdt_set_node_and_value(blob,
 666                                "/soc/cpm", "brg-frequency",
 667                                &brg_data, sizeof(brg_data));
 668
 669        /* MAC addr */
 670        if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 671                fdt_set_node_and_value(blob,
 672                                        "ethernet0", "local-mac-address",
 673                                        enetaddr, sizeof(u8) * 6);
 674        }
 675
 676        if (hwconfig_arg_cmp("fec", "off")) {
 677                /* no FEC on this plattform, delete DTS nodes */
 678                fdt_del_node_name (blob, "ethernet1");
 679                fdt_del_node_name (blob, "mdio1");
 680                /* also the aliases entries */
 681                fdt_del_prop_name (blob, "/aliases", "ethernet1");
 682                fdt_del_prop_name (blob, "/aliases", "mdio1");
 683        } else {
 684                /* adjust local-mac-address for FEC ethernet */
 685                if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
 686                        fdt_set_node_and_value(blob,
 687                                        "ethernet1", "local-mac-address",
 688                                        enetaddr, sizeof(u8) * 6);
 689                }
 690        }
 691}
 692
 693void ft_board_setup(void *blob, bd_t *bd)
 694{
 695        ft_cpu_setup(blob, bd);
 696        ft_blob_update(blob, bd);
 697}
 698#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
 699
 700/* ---------------------------------------------------------------------------- */
 701/* TK885D specific initializaion                                                */
 702/* ---------------------------------------------------------------------------- */
 703#ifdef CONFIG_TK885D
 704#include <miiphy.h>
 705int last_stage_init(void)
 706{
 707        const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
 708        unsigned short reg;
 709        int ret, i = 100;
 710        char *s;
 711
 712        mii_init();
 713        /* Without this delay 0xff is read from the UART buffer later in
 714         * abortboot() and autoboot is aborted */
 715        udelay(10000);
 716        while (tstc() && i--)
 717                (void)getc();
 718
 719        /* Check if auto-negotiation is prohibited */
 720        s = getenv("phy_auto_nego");
 721
 722        if (!s || !strcmp(s, "on"))
 723                /* Nothing to do - autonegotiation by default */
 724                return 0;
 725
 726        for (i = 0; i < 2; i++) {
 727                ret = miiphy_read("FEC", phy[i], MII_BMCR, &reg);
 728                if (ret) {
 729                        printf("Cannot read BMCR on PHY %d\n", phy[i]);
 730                        return 0;
 731                }
 732                /* Auto-negotiation off, hard set full duplex, 100Mbps */
 733                ret = miiphy_write("FEC", phy[i],
 734                                   MII_BMCR, (reg | BMCR_SPEED100 |
 735                                              BMCR_FULLDPLX) & ~BMCR_ANENABLE);
 736                if (ret) {
 737                        printf("Cannot write BMCR on PHY %d\n", phy[i]);
 738                        return 0;
 739                }
 740        }
 741
 742        return 0;
 743}
 744#endif
 745