1/* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#include <common.h> 25#include <i2c.h> 26 27#include <asm/fsl_ddr_sdram.h> 28#include <asm/fsl_ddr_dimm_params.h> 29 30void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) 31{ 32 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, 33 sizeof(ddr2_spd_eeprom_t)); 34} 35 36/* 37 * There are four board-specific SDRAM timing parameters which must be 38 * calculated based on the particular PCB artwork. These are: 39 * 1.) CPO (Read Capture Delay) 40 * - TIMING_CFG_2 register 41 * Source: Calculation based on board trace lengths and 42 * chip-specific internal delays. 43 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) 44 * - TIMING_CFG_2 register 45 * Source: Calculation based on board trace lengths. 46 * Unless clock and DQ lanes are very different 47 * lengths (>2"), this should be set to the nominal value 48 * of 1/2 clock delay. 49 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) 50 * - DDR_SDRAM_CLK_CNTL register 51 * Source: Signal Integrity Simulations 52 * 4.) 2T Timing on Addr/Ctl 53 * - TIMING_CFG_2 register 54 * Source: Signal Integrity Simulations 55 * Usually only needed with heavy load/very high speed (>DDR2-800) 56 * 57 * ====== XPedite5370 DDR2-600 read delay calculations ====== 58 * 59 * See Freescale's App Note AN2583 as refrence. This document also 60 * contains the chip-specific delays for 8548E, 8572, etc. 61 * 62 * For MPC8572E 63 * Minimum chip delay (Ch 0): 1.372ns 64 * Maximum chip delay (Ch 0): 2.914ns 65 * Minimum chip delay (Ch 1): 1.220ns 66 * Maximum chip delay (Ch 1): 2.595ns 67 * 68 * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps 69 * 70 * Minimum delay calc (Ch 0): 71 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 72 * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps 73 * = 3808ps 74 * = 3.808ns 75 * 76 * Maximum delay calc (Ch 0): 77 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly 78 * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps 79 * = 6240ps 80 * = 6.240ns 81 * 82 * Minimum delay calc (Ch 1): 83 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 84 * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps 85 * = 3288ps 86 * = 3.288ns 87 * 88 * Maximum delay calc (Ch 1): 89 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly 90 * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps 91 * = 5536ps 92 * = 5.536ns 93 * 94 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) 95 * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) 96 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) 97 * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) 98 * 99 * 100 * ====== XPedite5370 DDR2-800 read delay calculations ====== 101 * 102 * See Freescale's App Note AN2583 as refrence. This document also 103 * contains the chip-specific delays for 8548E, 8572, etc. 104 * 105 * For MPC8572E 106 * Minimum chip delay (Ch 0): 1.372ns 107 * Maximum chip delay (Ch 0): 2.914ns 108 * Minimum chip delay (Ch 1): 1.220ns 109 * Maximum chip delay (Ch 1): 2.595ns 110 * 111 * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps 112 * 113 * Minimum delay calc (Ch 0): 114 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 115 * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps 116 * = 3341ps 117 * = 3.341ns 118 * 119 * Maximum delay calc (Ch 0): 120 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly 121 * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps 122 * = 5673ps 123 * = 5.673ns 124 * 125 * Minimum delay calc (Ch 1): 126 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 127 * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps 128 * = 2822ps 129 * = 2.822ns 130 * 131 * Maximum delay calc (Ch 1): 132 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly 133 * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps 134 * = 4968ps 135 * = 4.968ns 136 * 137 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) 138 * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) 139 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) 140 * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) 141 * 142 * Write latency (WR_DATA_DELAY) is calculated by doing the following: 143 * 144 * The DDR SDRAM specification requires DQS be received no sooner than 145 * 75% of an SDRAM clock period—and no later than 125% of a clock 146 * period—from the capturing clock edge of the command/address at the 147 * SDRAM. 148 * 149 * Based on the above tracelengths, the following are calculated: 150 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns 151 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns 152 * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns 153 * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns 154 * 155 * Difference in arrival time CLK vs. DQS: 156 * Ch. 0 0.072ns 157 * Ch. 1 0.138ns 158 * 159 * Both of these values are much less than 25% of the clock 160 * period at DDR2-600 or DDR2-800, so no additional delay is needed over 161 * the 1/2 cycle which normally aligns the first DQS transition 162 * exactly WL (CAS latency minus one cycle) after the CAS strobe. 163 * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's 164 * terminology corresponds to exactly one clock period delay after 165 * the CAS strobe. (due to the fact that the "delay" is referenced 166 * from the *falling* edge of the CLK, just after the rising edge 167 * which the CAS strobe is latched on. 168 */ 169 170typedef struct board_memctl_options { 171 uint16_t datarate_mhz_low; 172 uint16_t datarate_mhz_high; 173 uint8_t clk_adjust; 174 uint8_t cpo_override; 175 uint8_t write_data_delay; 176} board_memctl_options_t; 177 178static struct board_memctl_options bopts_ctrl[][2] = { 179 { 180 /* Controller 0 */ 181 { 182 /* DDR2 600/667 */ 183 .datarate_mhz_low = 500, 184 .datarate_mhz_high = 750, 185 .clk_adjust = 5, 186 .cpo_override = 8, 187 .write_data_delay = 2, 188 }, 189 { 190 /* DDR2 800 */ 191 .datarate_mhz_low = 750, 192 .datarate_mhz_high = 850, 193 .clk_adjust = 5, 194 .cpo_override = 9, 195 .write_data_delay = 2, 196 }, 197 }, 198 { 199 /* Controller 1 */ 200 { 201 /* DDR2 600/667 */ 202 .datarate_mhz_low = 500, 203 .datarate_mhz_high = 750, 204 .clk_adjust = 5, 205 .cpo_override = 7, 206 .write_data_delay = 2, 207 }, 208 { 209 /* DDR2 800 */ 210 .datarate_mhz_low = 750, 211 .datarate_mhz_high = 850, 212 .clk_adjust = 5, 213 .cpo_override = 8, 214 .write_data_delay = 2, 215 }, 216 }, 217}; 218 219void fsl_ddr_board_options(memctl_options_t *popts, 220 dimm_params_t *pdimm, 221 unsigned int ctrl_num) 222{ 223 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; 224 sys_info_t sysinfo; 225 int i; 226 unsigned int datarate; 227 228 get_sys_info(&sysinfo); 229 datarate = sysinfo.freqDDRBus / 1000 / 1000; 230 231 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { 232 if ((bopts[i].datarate_mhz_low <= datarate) && 233 (bopts[i].datarate_mhz_high >= datarate)) { 234 debug("controller %d:\n", ctrl_num); 235 debug(" clk_adjust = %d\n", bopts[i].clk_adjust); 236 debug(" cpo = %d\n", bopts[i].cpo_override); 237 debug(" write_data_delay = %d\n", 238 bopts[i].write_data_delay); 239 popts->clk_adjust = bopts[i].clk_adjust; 240 popts->cpo_override = bopts[i].cpo_override; 241 popts->write_data_delay = bopts[i].write_data_delay; 242 } 243 } 244 245 /* 246 * Factors to consider for half-strength driver enable: 247 * - number of DIMMs installed 248 */ 249 popts->half_strength_driver_enable = 0; 250} 251