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14#ifndef MM_H
15#define MM_H
16
17#define __raw_readl readl
18#define __raw_writel writel
19
20#define BIG_ENDIAN_HOST 1
21#define readl(addr) (*(volatile unsigned int*)(addr))
22#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
23
24
25#define wmb()
26#define membar()
27#include <common.h>
28#include <asm/types.h>
29#include "bcm570x_lm.h"
30#include "bcm570x_queue.h"
31#include "tigon3.h"
32#include <pci.h>
33
34#define FALSE 0
35#define TRUE 1
36#define ERROR -1
37
38#if DBG
39#define STATIC
40#else
41#define STATIC static
42#endif
43
44extern int MM_Packet_Desc_Size;
45
46#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size
47
48DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1);
49
50#define MAX_MEM 16
51
52
53typedef int mutex_t;
54typedef int spinlock_t;
55
56
57typedef struct _UM_DEVICE_BLOCK {
58 LM_DEVICE_BLOCK lm_dev;
59 pci_dev_t pdev;
60 char *name;
61 void *mem_list[MAX_MEM];
62 dma_addr_t dma_list[MAX_MEM];
63 int mem_size_list[MAX_MEM];
64 int mem_list_num;
65 int mtu;
66 int index;
67 int opened;
68 int delayed_link_ind;
69 int adapter_just_inited;
70 int spurious_int;
71 int timer_interval;
72 int adaptive_expiry;
73 int crc_counter_expiry;
74 int poll_tib_expiry;
75 int tx_full;
76 int tx_queued;
77 int line_speed;
78 UM_RX_PACKET_Q rx_out_of_buf_q;
79 int rx_out_of_buf;
80 int rx_low_buf_thresh;
81 int rx_buf_repl_panic_thresh;
82 int rx_buf_align;
83 int do_global_lock;
84 mutex_t global_lock;
85 mutex_t undi_lock;
86 long undi_flags;
87 volatile int interrupt;
88 int tasklet_pending;
89 int tasklet_busy;
90 int rx_pkt;
91 int tx_pkt;
92#ifdef NICE_SUPPORT
93 void (*nice_rx) (void *, void *);
94 void *nice_ctx;
95#endif
96 int rx_adaptive_coalesce;
97 unsigned int rx_last_cnt;
98 unsigned int tx_last_cnt;
99 unsigned int rx_curr_coalesce_frames;
100 unsigned int rx_curr_coalesce_ticks;
101 unsigned int tx_curr_coalesce_frames;
102#if TIGON3_DEBUG
103 uint tx_zc_count;
104 uint tx_chksum_count;
105 uint tx_himem_count;
106 uint rx_good_chksum_count;
107#endif
108 unsigned int rx_bad_chksum_count;
109 unsigned int rx_misc_errors;
110} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
111
112
113typedef union {
114 dma_addr_t dma_map;
115} dma_map_t;
116
117
118typedef struct
119 _UM_PACKET {
120 LM_PACKET lm_packet;
121 void *skbuff;
122} UM_PACKET, *PUM_PACKET;
123
124#define MM_ACQUIRE_UNDI_LOCK(_pDevice)
125#define MM_RELEASE_UNDI_LOCK(_pDevice)
126#define MM_ACQUIRE_INT_LOCK(_pDevice)
127#define MM_RELEASE_INT_LOCK(_pDevice)
128#define MM_UINT_PTR(_ptr) ((unsigned long) (_ptr))
129
130
131#define set_64bit_addr(paddr, low, high) \
132 (paddr)->Low = low; \
133 (paddr)->High = high;
134
135
136
137#define MEM_TO_PCI_PHYS(addr) (addr)
138
139extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr);
140extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr);
141extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,
142 struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr,
143 LM_UINT32 * len, int frag);
144extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
145 struct _LM_PACKET *pPacket,
146 T3_64BIT_HOST_ADDR * paddr);
147
148
149extern void sysSerialPrintString (char *s);
150#define MM_Wait(usec) udelay(usec)
151
152
153#define wmb()
154
155#if 0
156#define cpu_to_le32(val) LONGSWAP(val)
157#endif
158#endif
159