1/* 2 * (X) extracted from enc28j60.c 3 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _enc28j60_h 22#define _enc28j60_h 23 24/* 25 * SPI Commands 26 * 27 * Bits 7-5: Command 28 * Bits 4-0: Register 29 */ 30#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */ 31#define CMD_RBM 0x3a /* Read Buffer Memory */ 32#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */ 33#define CMD_WBM 0x7a /* Write Buffer Memory */ 34#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */ 35#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */ 36#define CMD_SRC 0xff /* System Reset Command */ 37 38/* NEW: encode (bank number+1) in upper byte */ 39 40/* Common Control Registers accessible in all Banks */ 41#define CTL_REG_EIE 0x01B 42#define CTL_REG_EIR 0x01C 43#define CTL_REG_ESTAT 0x01D 44#define CTL_REG_ECON2 0x01E 45#define CTL_REG_ECON1 0x01F 46 47/* Control Registers accessible in Bank 0 */ 48#define CTL_REG_ERDPTL 0x100 49#define CTL_REG_ERDPTH 0x101 50#define CTL_REG_EWRPTL 0x102 51#define CTL_REG_EWRPTH 0x103 52#define CTL_REG_ETXSTL 0x104 53#define CTL_REG_ETXSTH 0x105 54#define CTL_REG_ETXNDL 0x106 55#define CTL_REG_ETXNDH 0x107 56#define CTL_REG_ERXSTL 0x108 57#define CTL_REG_ERXSTH 0x109 58#define CTL_REG_ERXNDL 0x10A 59#define CTL_REG_ERXNDH 0x10B 60#define CTL_REG_ERXRDPTL 0x10C 61#define CTL_REG_ERXRDPTH 0x10D 62#define CTL_REG_ERXWRPTL 0x10E 63#define CTL_REG_ERXWRPTH 0x10F 64#define CTL_REG_EDMASTL 0x110 65#define CTL_REG_EDMASTH 0x111 66#define CTL_REG_EDMANDL 0x112 67#define CTL_REG_EDMANDH 0x113 68#define CTL_REG_EDMADSTL 0x114 69#define CTL_REG_EDMADSTH 0x115 70#define CTL_REG_EDMACSL 0x116 71#define CTL_REG_EDMACSH 0x117 72 73/* Control Registers accessible in Bank 1 */ 74#define CTL_REG_EHT0 0x200 75#define CTL_REG_EHT1 0x201 76#define CTL_REG_EHT2 0x202 77#define CTL_REG_EHT3 0x203 78#define CTL_REG_EHT4 0x204 79#define CTL_REG_EHT5 0x205 80#define CTL_REG_EHT6 0x206 81#define CTL_REG_EHT7 0x207 82#define CTL_REG_EPMM0 0x208 83#define CTL_REG_EPMM1 0x209 84#define CTL_REG_EPMM2 0x20A 85#define CTL_REG_EPMM3 0x20B 86#define CTL_REG_EPMM4 0x20C 87#define CTL_REG_EPMM5 0x20D 88#define CTL_REG_EPMM6 0x20E 89#define CTL_REG_EPMM7 0x20F 90#define CTL_REG_EPMCSL 0x210 91#define CTL_REG_EPMCSH 0x211 92#define CTL_REG_EPMOL 0x214 93#define CTL_REG_EPMOH 0x215 94#define CTL_REG_EWOLIE 0x216 95#define CTL_REG_EWOLIR 0x217 96#define CTL_REG_ERXFCON 0x218 97#define CTL_REG_EPKTCNT 0x219 98 99/* Control Registers accessible in Bank 2 */ 100#define CTL_REG_MACON1 0x300 101#define CTL_REG_MACON2 0x301 102#define CTL_REG_MACON3 0x302 103#define CTL_REG_MACON4 0x303 104#define CTL_REG_MABBIPG 0x304 105#define CTL_REG_MAIPGL 0x306 106#define CTL_REG_MAIPGH 0x307 107#define CTL_REG_MACLCON1 0x308 108#define CTL_REG_MACLCON2 0x309 109#define CTL_REG_MAMXFLL 0x30A 110#define CTL_REG_MAMXFLH 0x30B 111#define CTL_REG_MAPHSUP 0x30D 112#define CTL_REG_MICON 0x311 113#define CTL_REG_MICMD 0x312 114#define CTL_REG_MIREGADR 0x314 115#define CTL_REG_MIWRL 0x316 116#define CTL_REG_MIWRH 0x317 117#define CTL_REG_MIRDL 0x318 118#define CTL_REG_MIRDH 0x319 119 120/* Control Registers accessible in Bank 3 */ 121#define CTL_REG_MAADR1 0x400 122#define CTL_REG_MAADR0 0x401 123#define CTL_REG_MAADR3 0x402 124#define CTL_REG_MAADR2 0x403 125#define CTL_REG_MAADR5 0x404 126#define CTL_REG_MAADR4 0x405 127#define CTL_REG_EBSTSD 0x406 128#define CTL_REG_EBSTCON 0x407 129#define CTL_REG_EBSTCSL 0x408 130#define CTL_REG_EBSTCSH 0x409 131#define CTL_REG_MISTAT 0x40A 132#define CTL_REG_EREVID 0x412 133#define CTL_REG_ECOCON 0x415 134#define CTL_REG_EFLOCON 0x417 135#define CTL_REG_EPAUSL 0x418 136#define CTL_REG_EPAUSH 0x419 137 138/* PHY Register */ 139#define PHY_REG_PHCON1 0x00 140#define PHY_REG_PHSTAT1 0x01 141#define PHY_REG_PHID1 0x02 142#define PHY_REG_PHID2 0x03 143#define PHY_REG_PHCON2 0x10 144#define PHY_REG_PHSTAT2 0x11 145#define PHY_REG_PHLCON 0x14 146 147/* Receive Filter Register (ERXFCON) bits */ 148#define ENC_RFR_UCEN 0x80 149#define ENC_RFR_ANDOR 0x40 150#define ENC_RFR_CRCEN 0x20 151#define ENC_RFR_PMEN 0x10 152#define ENC_RFR_MPEN 0x08 153#define ENC_RFR_HTEN 0x04 154#define ENC_RFR_MCEN 0x02 155#define ENC_RFR_BCEN 0x01 156 157/* ECON1 Register Bits */ 158#define ENC_ECON1_TXRST 0x80 159#define ENC_ECON1_RXRST 0x40 160#define ENC_ECON1_DMAST 0x20 161#define ENC_ECON1_CSUMEN 0x10 162#define ENC_ECON1_TXRTS 0x08 163#define ENC_ECON1_RXEN 0x04 164#define ENC_ECON1_BSEL1 0x02 165#define ENC_ECON1_BSEL0 0x01 166 167/* ECON2 Register Bits */ 168#define ENC_ECON2_AUTOINC 0x80 169#define ENC_ECON2_PKTDEC 0x40 170#define ENC_ECON2_PWRSV 0x20 171#define ENC_ECON2_VRPS 0x08 172 173/* EIR Register Bits */ 174#define ENC_EIR_PKTIF 0x40 175#define ENC_EIR_DMAIF 0x20 176#define ENC_EIR_LINKIF 0x10 177#define ENC_EIR_TXIF 0x08 178#define ENC_EIR_WOLIF 0x04 179#define ENC_EIR_TXERIF 0x02 180#define ENC_EIR_RXERIF 0x01 181 182/* ESTAT Register Bits */ 183#define ENC_ESTAT_INT 0x80 184#define ENC_ESTAT_LATECOL 0x10 185#define ENC_ESTAT_RXBUSY 0x04 186#define ENC_ESTAT_TXABRT 0x02 187#define ENC_ESTAT_CLKRDY 0x01 188 189/* EIE Register Bits */ 190#define ENC_EIE_INTIE 0x80 191#define ENC_EIE_PKTIE 0x40 192#define ENC_EIE_DMAIE 0x20 193#define ENC_EIE_LINKIE 0x10 194#define ENC_EIE_TXIE 0x08 195#define ENC_EIE_WOLIE 0x04 196#define ENC_EIE_TXERIE 0x02 197#define ENC_EIE_RXERIE 0x01 198 199/* MACON1 Register Bits */ 200#define ENC_MACON1_LOOPBK 0x10 201#define ENC_MACON1_TXPAUS 0x08 202#define ENC_MACON1_RXPAUS 0x04 203#define ENC_MACON1_PASSALL 0x02 204#define ENC_MACON1_MARXEN 0x01 205 206/* MACON2 Register Bits */ 207#define ENC_MACON2_MARST 0x80 208#define ENC_MACON2_RNDRST 0x40 209#define ENC_MACON2_MARXRST 0x08 210#define ENC_MACON2_RFUNRST 0x04 211#define ENC_MACON2_MATXRST 0x02 212#define ENC_MACON2_TFUNRST 0x01 213 214/* MACON3 Register Bits */ 215#define ENC_MACON3_PADCFG2 0x80 216#define ENC_MACON3_PADCFG1 0x40 217#define ENC_MACON3_PADCFG0 0x20 218#define ENC_MACON3_TXCRCEN 0x10 219#define ENC_MACON3_PHDRLEN 0x08 220#define ENC_MACON3_HFRMEN 0x04 221#define ENC_MACON3_FRMLNEN 0x02 222#define ENC_MACON3_FULDPX 0x01 223 224/* MACON4 Register Bits */ 225#define ENC_MACON4_DEFER 0x40 226 227/* MICMD Register Bits */ 228#define ENC_MICMD_MIISCAN 0x02 229#define ENC_MICMD_MIIRD 0x01 230 231/* MISTAT Register Bits */ 232#define ENC_MISTAT_NVALID 0x04 233#define ENC_MISTAT_SCAN 0x02 234#define ENC_MISTAT_BUSY 0x01 235 236/* PHID1 and PHID2 values */ 237#define ENC_PHID1_VALUE 0x0083 238#define ENC_PHID2_VALUE 0x1400 239#define ENC_PHID2_MASK 0xFC00 240 241/* PHCON1 values */ 242#define ENC_PHCON1_PDPXMD 0x0100 243 244/* PHSTAT1 values */ 245#define ENC_PHSTAT1_LLSTAT 0x0004 246 247/* PHSTAT2 values */ 248#define ENC_PHSTAT2_LSTAT 0x0400 249#define ENC_PHSTAT2_DPXSTAT 0x0200 250 251#endif 252