1/* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _M5235EVB_H 31#define _M5235EVB_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MCF523x /* define processor family */ 38#define CONFIG_M5235 /* define processor type */ 39 40#define CONFIG_MCFUART 41#define CONFIG_SYS_UART_PORT (0) 42#define CONFIG_BAUDRATE 115200 43#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 44 45#undef CONFIG_WATCHDOG 46#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 47 48/* 49 * BOOTP options 50 */ 51#define CONFIG_BOOTP_BOOTFILESIZE 52#define CONFIG_BOOTP_BOOTPATH 53#define CONFIG_BOOTP_GATEWAY 54#define CONFIG_BOOTP_HOSTNAME 55 56/* Command line configuration */ 57#include <config_cmd_default.h> 58 59#define CONFIG_CMD_BOOTD 60#define CONFIG_CMD_CACHE 61#define CONFIG_CMD_DHCP 62#define CONFIG_CMD_ELF 63#define CONFIG_CMD_FLASH 64#define CONFIG_CMD_I2C 65#define CONFIG_CMD_MEMORY 66#define CONFIG_CMD_MISC 67#define CONFIG_CMD_MII 68#define CONFIG_CMD_NET 69#define CONFIG_CMD_PCI 70#define CONFIG_CMD_PING 71#define CONFIG_CMD_REGINFO 72 73#undef CONFIG_CMD_LOADB 74#undef CONFIG_CMD_LOADS 75 76#define CONFIG_MCFFEC 77#ifdef CONFIG_MCFFEC 78# define CONFIG_NET_MULTI 1 79# define CONFIG_MII 1 80# define CONFIG_MII_INIT 1 81# define CONFIG_SYS_DISCOVER_PHY 82# define CONFIG_SYS_RX_ETH_BUFFER 8 83# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 84 85# define CONFIG_SYS_FEC0_PINMUX 0 86# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 87# define MCFFEC_TOUT_LOOP 50000 88/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 89# ifndef CONFIG_SYS_DISCOVER_PHY 90# define FECDUPLEX FULL 91# define FECSPEED _100BASET 92# else 93# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 94# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 95# endif 96# endif /* CONFIG_SYS_DISCOVER_PHY */ 97#endif 98 99/* Timer */ 100#define CONFIG_MCFTMR 101#undef CONFIG_MCFPIT 102 103/* I2C */ 104#define CONFIG_FSL_I2C 105#define CONFIG_HARD_I2C /* I2C with hw support */ 106#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 107#define CONFIG_SYS_I2C_SPEED 80000 108#define CONFIG_SYS_I2C_SLAVE 0x7F 109#define CONFIG_SYS_I2C_OFFSET 0x00000300 110#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 111#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 112#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 113#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 114 115/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 116#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 117#define CONFIG_BOOTFILE "u-boot.bin" 118#ifdef CONFIG_MCFFEC 119# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 120# define CONFIG_IPADDR 192.162.1.2 121# define CONFIG_NETMASK 255.255.255.0 122# define CONFIG_SERVERIP 192.162.1.1 123# define CONFIG_GATEWAYIP 192.162.1.1 124# define CONFIG_OVERWRITE_ETHADDR_ONCE 125#endif /* FEC_ENET */ 126 127#define CONFIG_HOSTNAME M5235EVB 128#define CONFIG_EXTRA_ENV_SETTINGS \ 129 "netdev=eth0\0" \ 130 "loadaddr=10000\0" \ 131 "u-boot=u-boot.bin\0" \ 132 "load=tftp ${loadaddr) ${u-boot}\0" \ 133 "upd=run load; run prog\0" \ 134 "prog=prot off ffe00000 ffe3ffff;" \ 135 "era ffe00000 ffe3ffff;" \ 136 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 137 "save\0" \ 138 "" 139 140#define CONFIG_PRAM 512 /* 512 KB */ 141#define CONFIG_SYS_PROMPT "-> " 142#define CONFIG_SYS_LONGHELP /* undef to save memory */ 143 144#if defined(CONFIG_KGDB) 145# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 146#else 147# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 148#endif 149 150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 151#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 153#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 154 155#define CONFIG_SYS_HZ 1000 156#define CONFIG_SYS_CLK 75000000 157#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 158 159#define CONFIG_SYS_MBAR 0x40000000 160 161/* 162 * Low Level Configuration Settings 163 * (address mappings, register initial values, etc.) 164 * You should know what you are doing if you make changes here. 165 */ 166/*----------------------------------------------------------------------- 167 * Definitions for initial stack pointer and data area (in DPRAM) 168 */ 169#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 170#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 171#define CONFIG_SYS_INIT_RAM_CTRL 0x21 172#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 173#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 174 175/*----------------------------------------------------------------------- 176 * Start addresses for the final memory configuration 177 * (Set up by the startup code) 178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 179 */ 180#define CONFIG_SYS_SDRAM_BASE 0x00000000 181#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 182 183#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 184#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 185 186#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 187#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188 189#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 190#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 191 192/* 193 * For booting Linux, the board info and command line data 194 * have to be in the first 8 MB of memory, since this is 195 * the maximum mapped by the Linux kernel during initialization ?? 196 */ 197/* Initial Memory map for Linux */ 198#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 199#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 200 201/*----------------------------------------------------------------------- 202 * FLASH organization 203 */ 204#define CONFIG_SYS_FLASH_CFI 205#ifdef CONFIG_SYS_FLASH_CFI 206# define CONFIG_FLASH_CFI_DRIVER 1 207# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 208#ifdef NORFLASH_PS32BIT 209# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 210#else 211# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 212#endif 213# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 214# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 215# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 216#endif 217 218#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 219 220/* Configuration for environment 221 * Environment is embedded in u-boot in the second sector of the flash 222 */ 223#define CONFIG_ENV_IS_IN_FLASH 1 224#ifdef NORFLASH_PS32BIT 225# define CONFIG_ENV_OFFSET (0x8000) 226# define CONFIG_ENV_SIZE 0x4000 227# define CONFIG_ENV_SECT_SIZE 0x4000 228#else 229# define CONFIG_ENV_OFFSET (0x4000) 230# define CONFIG_ENV_SIZE 0x2000 231# define CONFIG_ENV_SECT_SIZE 0x2000 232#endif 233 234/*----------------------------------------------------------------------- 235 * Cache Configuration 236 */ 237#define CONFIG_SYS_CACHELINE_SIZE 16 238 239#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 240 CONFIG_SYS_INIT_RAM_SIZE - 8) 241#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 242 CONFIG_SYS_INIT_RAM_SIZE - 4) 243#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 244#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 245 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 246 CF_ACR_EN | CF_ACR_SM_ALL) 247#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 248 CF_CACR_CEIB | CF_CACR_DCM | \ 249 CF_CACR_EUSP) 250 251/*----------------------------------------------------------------------- 252 * Chipselect bank definitions 253 */ 254/* 255 * CS0 - NOR Flash 1, 2, 4, or 8MB 256 * CS1 - Available 257 * CS2 - Available 258 * CS3 - Available 259 * CS4 - Available 260 * CS5 - Available 261 * CS6 - Available 262 * CS7 - Available 263 */ 264#ifdef NORFLASH_PS32BIT 265# define CONFIG_SYS_CS0_BASE 0xFFC00000 266# define CONFIG_SYS_CS0_MASK 0x003f0001 267# define CONFIG_SYS_CS0_CTRL 0x00001D00 268#else 269# define CONFIG_SYS_CS0_BASE 0xFFE00000 270# define CONFIG_SYS_CS0_MASK 0x001f0001 271# define CONFIG_SYS_CS0_CTRL 0x00001D80 272#endif 273 274#endif /* _M5329EVB_H */ 275