1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25
26
27
28#define CONFIG_E300 1
29#define CONFIG_QE 1
30#define CONFIG_MPC83xx 1
31#define CONFIG_MPC8360 1
32#define CONFIG_MPC8360EMDS 1
33
34#define CONFIG_SYS_TEXT_BASE 0xFE000000
35
36#undef CONFIG_PQ_MDS_PIB
37#undef CONFIG_PQ_MDS_PIB_ATM
38
39
40
41
42#ifdef CONFIG_PCISLAVE
43#define CONFIG_83XX_PCICLK 66000000
44#else
45#define CONFIG_83XX_CLKIN 66000000
46#endif
47
48#ifndef CONFIG_SYS_CLK_FREQ
49#define CONFIG_SYS_CLK_FREQ 66000000
50#endif
51
52
53
54
55#define CONFIG_SYS_HRCW_LOW (\
56 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
57 HRCWL_DDR_TO_SCB_CLK_1X1 |\
58 HRCWL_CSB_TO_CLKIN_4X1 |\
59 HRCWL_VCO_1X2 |\
60 HRCWL_CE_PLL_VCO_DIV_4 |\
61 HRCWL_CE_PLL_DIV_1X1 |\
62 HRCWL_CE_TO_PLL_1X6 |\
63 HRCWL_CORE_TO_CSB_2X1)
64
65#ifdef CONFIG_PCISLAVE
66#define CONFIG_SYS_HRCW_HIGH (\
67 HRCWH_PCI_AGENT |\
68 HRCWH_PCI1_ARBITER_DISABLE |\
69 HRCWH_PCICKDRV_DISABLE |\
70 HRCWH_CORE_ENABLE |\
71 HRCWH_FROM_0XFFF00100 |\
72 HRCWH_BOOTSEQ_DISABLE |\
73 HRCWH_SW_WATCHDOG_DISABLE |\
74 HRCWH_ROM_LOC_LOCAL_16BIT)
75#else
76#define CONFIG_SYS_HRCW_HIGH (\
77 HRCWH_PCI_HOST |\
78 HRCWH_PCI1_ARBITER_ENABLE |\
79 HRCWH_PCICKDRV_ENABLE |\
80 HRCWH_CORE_ENABLE |\
81 HRCWH_FROM_0X00000100 |\
82 HRCWH_BOOTSEQ_DISABLE |\
83 HRCWH_SW_WATCHDOG_DISABLE |\
84 HRCWH_ROM_LOC_LOCAL_16BIT)
85#endif
86
87
88
89
90#define CONFIG_SYS_SICRH 0x00000000
91#define CONFIG_SYS_SICRL 0x40000000
92
93#define CONFIG_BOARD_EARLY_INIT_F
94#define CONFIG_BOARD_EARLY_INIT_R
95
96
97
98
99#define CONFIG_SYS_IMMR 0xE0000000
100
101
102
103
104#define CONFIG_SYS_DDR_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
106#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
107#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
108#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
109 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
110
111#define CONFIG_SYS_83XX_DDR_USES_CS0
112
113#define CONFIG_DDR_ECC
114#define CONFIG_DDR_ECC_CMD
115
116
117
118
119#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
120
121#define CONFIG_SPD_EEPROM
122#if defined(CONFIG_SPD_EEPROM)
123
124
125
126#define SPD_EEPROM_ADDRESS 0x52
127#else
128
129
130
131#define CONFIG_SYS_DDR_SIZE 256
132#if defined(CONFIG_DDR_II)
133#define CONFIG_SYS_DDRCDR 0x80080001
134#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
135#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
136#define CONFIG_SYS_DDR_TIMING_0 0x00220802
137#define CONFIG_SYS_DDR_TIMING_1 0x38357322
138#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
139#define CONFIG_SYS_DDR_TIMING_3 0x00000000
140#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
141#define CONFIG_SYS_DDR_MODE 0x47d00432
142#define CONFIG_SYS_DDR_MODE2 0x8000c000
143#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
144#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
145#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
146#else
147#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
148#define CONFIG_SYS_DDR_TIMING_1 0x37344321
149#define CONFIG_SYS_DDR_TIMING_2 0x00000800
150#define CONFIG_SYS_DDR_CONTROL 0x42008000
151#define CONFIG_SYS_DDR_MODE 0x20000162
152#define CONFIG_SYS_DDR_INTERVAL 0x045b0100
153#endif
154#endif
155
156
157
158
159#undef CONFIG_SYS_DRAM_TEST
160#define CONFIG_SYS_MEMTEST_START 0x00000000
161#define CONFIG_SYS_MEMTEST_END 0x00100000
162
163
164
165
166
167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
168
169#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
170#define CONFIG_SYS_RAMBOOT
171#else
172#undef CONFIG_SYS_RAMBOOT
173#endif
174
175
176#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
177#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
178
179
180
181
182#define CONFIG_SYS_INIT_RAM_LOCK 1
183#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
184#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
185#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186
187
188
189
190#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
191#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
192#define CONFIG_SYS_LBC_LBCR 0x00000000
193
194
195
196
197#define CONFIG_SYS_FLASH_CFI
198#define CONFIG_FLASH_CFI_DRIVER
199#define CONFIG_SYS_FLASH_BASE 0xFE000000
200#define CONFIG_SYS_FLASH_SIZE 32
201#define CONFIG_SYS_FLASH_PROTECTION 1
202#define CONFIG_FLASH_SHOW_PROGRESS 45
203
204#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
205#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018
206
207#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
208 (2 << BR_PS_SHIFT) | \
209 BR_V)
210#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
211 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
212 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
213
214#define CONFIG_SYS_MAX_FLASH_BANKS 1
215#define CONFIG_SYS_MAX_FLASH_SECT 256
216
217#undef CONFIG_SYS_FLASH_CHECKSUM
218
219
220
221
222#define CONFIG_SYS_BCSR 0xF8000000
223#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
224#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F
225
226#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801)
227#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7
228
229
230
231
232#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
233#define CONFIG_SYS_LBC_SDRAM_SIZE 64
234
235#define CONFIG_SYS_LB_SDRAM
236
237#ifdef CONFIG_SYS_LB_SDRAM
238#define CONFIG_SYS_LBLAWBAR2 0
239#define CONFIG_SYS_LBLAWAR2 0x80000019
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256#define CONFIG_SYS_BR2 0x00001861
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272#define CONFIG_SYS_OR2 0xfc006901
273
274#define CONFIG_SYS_LBC_LSRT 0x32000000
275#define CONFIG_SYS_LBC_MRTPR 0x20000000
276
277#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
278
279
280
281
282#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
283#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
284#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
285#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
286#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
287
288#endif
289
290
291
292
293#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000
294#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e
295
296
297
298
299#define CONFIG_SYS_BR4_PRELIM 0xf8008801
300#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
301
302
303
304
305#define CONFIG_SYS_BR5_PRELIM 0xf8010801
306#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
307
308
309
310
311#define CONFIG_CONS_INDEX 1
312#define CONFIG_SYS_NS16550
313#define CONFIG_SYS_NS16550_SERIAL
314#define CONFIG_SYS_NS16550_REG_SIZE 1
315#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
316
317#define CONFIG_SYS_BAUDRATE_TABLE \
318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
319
320#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
321#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
322
323#define CONFIG_CMDLINE_EDITING 1
324#define CONFIG_AUTO_COMPLETE
325
326#define CONFIG_SYS_HUSH_PARSER
327#ifdef CONFIG_SYS_HUSH_PARSER
328#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
329#endif
330
331
332#define CONFIG_OF_LIBFDT 1
333#define CONFIG_OF_BOARD_SETUP 1
334#define CONFIG_OF_STDOUT_VIA_ALIAS 1
335
336
337#define CONFIG_HARD_I2C
338#undef CONFIG_SOFT_I2C
339#define CONFIG_FSL_I2C
340#define CONFIG_SYS_I2C_SPEED 400000
341#define CONFIG_SYS_I2C_SLAVE 0x7F
342#define CONFIG_SYS_I2C_NOPROBES {0x52}
343#define CONFIG_SYS_I2C_OFFSET 0x3000
344#define CONFIG_SYS_I2C2_OFFSET 0x3100
345
346
347
348
349#define CONFIG_RTC_DS1374
350#define CONFIG_SYS_I2C_RTC_ADDR 0x68
351
352
353
354
355
356#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
357#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
358#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
359#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
360#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
361#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
362#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
363#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
364#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
365
366#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
367#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
368#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
369
370
371#ifdef CONFIG_PCI
372
373#define CONFIG_NET_MULTI
374#define CONFIG_PCI_PNP
375#define CONFIG_83XX_PCI_STREAMING
376
377#undef CONFIG_EEPRO100
378#undef CONFIG_PCI_SCAN_SHOW
379#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
380
381#endif
382
383
384#ifndef CONFIG_NET_MULTI
385#define CONFIG_NET_MULTI 1
386#endif
387
388#define CONFIG_HWCONFIG 1
389
390
391
392
393#define CONFIG_UEC_ETH
394#define CONFIG_ETHPRIME "UEC0"
395#define CONFIG_PHY_MODE_NEED_CHANGE
396
397#define CONFIG_UEC_ETH1
398
399#ifdef CONFIG_UEC_ETH1
400#define CONFIG_SYS_UEC1_UCC_NUM 0
401#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
402#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
403#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
404#define CONFIG_SYS_UEC1_PHY_ADDR 0
405#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
406#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
407#endif
408
409#define CONFIG_UEC_ETH2
410
411#ifdef CONFIG_UEC_ETH2
412#define CONFIG_SYS_UEC2_UCC_NUM 1
413#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
414#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
415#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
416#define CONFIG_SYS_UEC2_PHY_ADDR 1
417#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
418#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
419#endif
420
421
422
423
424
425#ifndef CONFIG_SYS_RAMBOOT
426 #define CONFIG_ENV_IS_IN_FLASH 1
427 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
428 #define CONFIG_ENV_SECT_SIZE 0x20000
429 #define CONFIG_ENV_SIZE 0x2000
430#else
431 #define CONFIG_SYS_NO_FLASH 1
432 #define CONFIG_ENV_IS_NOWHERE 1
433 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
434 #define CONFIG_ENV_SIZE 0x2000
435#endif
436
437#define CONFIG_LOADS_ECHO 1
438#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
439
440
441
442
443#define CONFIG_BOOTP_BOOTFILESIZE
444#define CONFIG_BOOTP_BOOTPATH
445#define CONFIG_BOOTP_GATEWAY
446#define CONFIG_BOOTP_HOSTNAME
447
448
449
450
451
452#include <config_cmd_default.h>
453
454#define CONFIG_CMD_PING
455#define CONFIG_CMD_I2C
456#define CONFIG_CMD_ASKENV
457#define CONFIG_CMD_SDRAM
458
459#if defined(CONFIG_PCI)
460 #define CONFIG_CMD_PCI
461#endif
462
463#if defined(CONFIG_SYS_RAMBOOT)
464 #undef CONFIG_CMD_SAVEENV
465 #undef CONFIG_CMD_LOADS
466#endif
467
468
469#undef CONFIG_WATCHDOG
470
471
472
473
474#define CONFIG_SYS_LONGHELP
475#define CONFIG_SYS_LOAD_ADDR 0x2000000
476#define CONFIG_SYS_PROMPT "=> "
477
478#if defined(CONFIG_CMD_KGDB)
479 #define CONFIG_SYS_CBSIZE 1024
480#else
481 #define CONFIG_SYS_CBSIZE 256
482#endif
483
484#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
485#define CONFIG_SYS_MAXARGS 16
486#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
487#define CONFIG_SYS_HZ 1000
488
489
490
491
492
493
494#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
495
496
497
498
499#define CONFIG_SYS_HID0_INIT 0x000000000
500#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
501 HID0_ENABLE_INSTRUCTION_CACHE)
502#define CONFIG_SYS_HID2 HID2_HBE
503
504
505
506
507
508#define CONFIG_HIGH_BATS 1
509
510
511#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
512#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
513#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
514#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
515
516
517#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
518 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
519#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
520#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
521#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
522
523
524#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
525 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
526#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
527#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
528#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
529
530
531#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
532#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
533#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
534 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
535#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
536
537
538#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
539#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
540#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
541#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
542
543
544#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
545#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
546#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
547#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
548
549#ifdef CONFIG_PCI
550
551#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
552#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
553#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
554#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
555
556#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
557 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
558#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
559#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
560#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
561#else
562#define CONFIG_SYS_IBAT6L (0)
563#define CONFIG_SYS_IBAT6U (0)
564#define CONFIG_SYS_IBAT7L (0)
565#define CONFIG_SYS_IBAT7U (0)
566#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
567#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
568#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
569#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
570#endif
571
572#if defined(CONFIG_CMD_KGDB)
573#define CONFIG_KGDB_BAUDRATE 230400
574#define CONFIG_KGDB_SER_INDEX 2
575#endif
576
577
578
579
580
581#define CONFIG_ENV_OVERWRITE
582
583#if defined(CONFIG_UEC_ETH)
584#define CONFIG_HAS_ETH0
585#define CONFIG_HAS_ETH1
586#endif
587
588#define CONFIG_BAUDRATE 115200
589
590#define CONFIG_LOADADDR 800000
591
592#define CONFIG_BOOTDELAY 6
593#undef CONFIG_BOOTARGS
594
595#define CONFIG_EXTRA_ENV_SETTINGS \
596 "netdev=eth0\0" \
597 "consoledev=ttyS0\0" \
598 "ramdiskaddr=1000000\0" \
599 "ramdiskfile=ramfs.83xx\0" \
600 "fdtaddr=780000\0" \
601 "fdtfile=mpc836x_mds.dtb\0" \
602 ""
603
604#define CONFIG_NFSBOOTCOMMAND \
605 "setenv bootargs root=/dev/nfs rw " \
606 "nfsroot=$serverip:$rootpath " \
607 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
608 "console=$consoledev,$baudrate $othbootargs;" \
609 "tftp $loadaddr $bootfile;" \
610 "tftp $fdtaddr $fdtfile;" \
611 "bootm $loadaddr - $fdtaddr"
612
613#define CONFIG_RAMBOOTCOMMAND \
614 "setenv bootargs root=/dev/ram rw " \
615 "console=$consoledev,$baudrate $othbootargs;" \
616 "tftp $ramdiskaddr $ramdiskfile;" \
617 "tftp $loadaddr $bootfile;" \
618 "tftp $fdtaddr $fdtfile;" \
619 "bootm $loadaddr $ramdiskaddr $fdtaddr"
620
621
622#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
623
624#endif
625