1/* 2 * (C) Copyright 2003-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 23 */ 24 25/************************************************************************* 26 * (c) 2005 esd gmbh Hannover 27 * 28 * 29 * from IceCube.h file 30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com 31 * 32 *************************************************************************/ 33 34#ifndef __CONFIG_H 35#define __CONFIG_H 36 37/* 38 * High Level Configuration Options 39 * (easy to change) 40 */ 41 42#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ 43#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 44#define CONFIG_ICECUBE 1 /* ... on IceCube board */ 45#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */ 46#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ 47 48#ifndef CONFIG_SYS_TEXT_BASE 49#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ 50#endif 51 52#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 53 54#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 55 56/* 57 * Serial console configuration 58 */ 59#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 60#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ 61#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 62 63/* 64 * PCI Mapping: 65 * 0x40000000 - 0x4fffffff - PCI Memory 66 * 0x50000000 - 0x50ffffff - PCI IO Space 67 */ 68#if 1 69#define CONFIG_PCI 1 70#if 1 71#define CONFIG_PCI_PNP 1 72#endif 73#define CONFIG_PCI_SCAN_SHOW 1 74#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 75 76#define CONFIG_PCI_MEM_BUS 0x40000000 77#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 78#define CONFIG_PCI_MEM_SIZE 0x10000000 79 80#define CONFIG_PCI_IO_BUS 0x50000000 81#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 82#define CONFIG_PCI_IO_SIZE 0x01000000 83#endif 84 85#define CONFIG_MII 86#if 0 /* test-only !!! */ 87#define CONFIG_NET_MULTI 1 88#define CONFIG_EEPRO100 1 89#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 90#define CONFIG_NS8382X 1 91#endif 92 93/* Partitions */ 94#define CONFIG_MAC_PARTITION 95#define CONFIG_DOS_PARTITION 96 97/* USB */ 98#if 0 99#define CONFIG_USB_OHCI 100#define CONFIG_USB_STORAGE 101#endif 102 103/* 104 * BOOTP options 105 */ 106#define CONFIG_BOOTP_BOOTFILESIZE 107#define CONFIG_BOOTP_BOOTPATH 108#define CONFIG_BOOTP_GATEWAY 109#define CONFIG_BOOTP_HOSTNAME 110 111 112/* 113 * Command line configuration. 114 */ 115#include <config_cmd_default.h> 116 117#if defined(CONFIG_PCI) 118#define CONFIG_CMD_PCI 119#endif 120 121#define CONFIG_CMD_EEPROM 122#define CONFIG_CMD_FAT 123#define CONFIG_CMD_IDE 124#define CONFIG_CMD_I2C 125#define CONFIG_CMD_BSP 126#define CONFIG_CMD_ELF 127#define CONFIG_CMD_EXT2 128#define CONFIG_CMD_DATE 129 130#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ 131# define CONFIG_SYS_LOWBOOT 1 132# define CONFIG_SYS_LOWBOOT16 1 133#endif 134#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ 135# define CONFIG_SYS_LOWBOOT 1 136# define CONFIG_SYS_LOWBOOT08 1 137#endif 138 139/* 140 * Autobooting 141 */ 142#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 143 144#define CONFIG_PREBOOT "echo;" \ 145 "echo Welcome to esd CPU CPCI/5200;" \ 146 "echo" 147 148#undef CONFIG_BOOTARGS 149 150#define CONFIG_EXTRA_ENV_SETTINGS \ 151 "netdev=eth0\0" \ 152 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ 153 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ 154 "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ 155 "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ 156 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ 157 "loadaddr=01000000\0" \ 158 "serverip=192.168.2.99\0" \ 159 "gatewayip=10.0.0.79\0" \ 160 "user=mu\0" \ 161 "target=cpci5200.esd\0" \ 162 "script=cpci5200.bat\0" \ 163 "image=/tftpboot/vxWorks_cpci5200\0" \ 164 "ipaddr=10.0.13.196\0" \ 165 "netmask=255.255.0.0\0" \ 166 "" 167 168#define CONFIG_BOOTCOMMAND "run flash_vxworks0" 169 170#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ 171#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000 172#define CONFIG_SYS_NVRAM_SIZE 32*1024 173 174/* 175 * IPB Bus clocking configuration. 176 */ 177#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 178/* 179 * I2C configuration 180 */ 181#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 182#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ 183 184#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ 185#define CONFIG_SYS_I2C_SLAVE 0x7F 186 187/* 188 * EEPROM configuration 189 */ 190#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 191#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 192#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 193#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 194#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 195/* 196 * Flash configuration 197 */ 198 199#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 200#define CONFIG_SYS_FLASH_BASE 0xFE000000 201#define CONFIG_SYS_FLASH_SIZE 0x02000000 202#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 203#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) 204#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 205#define CONFIG_SYS_MAX_FLASH_SECT 128 206 207#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ 208#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 209 210#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 211#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 212 213/* 214 * Environment settings 215 */ 216#if 1 /* test-only */ 217#define CONFIG_ENV_IS_IN_FLASH 1 218#define CONFIG_ENV_SIZE 0x20000 219#define CONFIG_ENV_SECT_SIZE 0x20000 220#define CONFIG_ENV_OVERWRITE 1 221#else 222#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 223#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ 224#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ 225 /* total size of a CAT24WC32 is 8192 bytes */ 226#define CONFIG_ENV_OVERWRITE 1 227#endif 228 229/* 230 * Memory map 231 */ 232#define CONFIG_SYS_MBAR 0xF0000000 233#define CONFIG_SYS_SDRAM_BASE 0x00000000 234#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 235 236/* Use SRAM until RAM will be available */ 237#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 238#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 239 240#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 242 243#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 244#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 245# define CONFIG_SYS_RAMBOOT 1 246#endif 247 248#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 249#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 250#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 251 252/* 253 * Ethernet configuration 254 */ 255#define CONFIG_MPC5xxx_FEC 1 256#define CONFIG_MPC5xxx_FEC_MII100 257/* 258 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb 259 */ 260/* #define CONFIG_FEC_10MBIT 1 */ 261#define CONFIG_PHY_ADDR 0x00 262#define CONFIG_UDP_CHECKSUM 1 263 264/* 265 * GPIO configuration 266 */ 267#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 268 269/* 270 * Miscellaneous configurable options 271 */ 272#define CONFIG_SYS_LONGHELP /* undef to save memory */ 273#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 274#if defined(CONFIG_CMD_KGDB) 275#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 276#else 277#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 278#endif 279#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 280#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 281#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 282 283#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 284#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 285 286#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 287 288#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 289 290#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ 291 292#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 293#if defined(CONFIG_CMD_KGDB) 294# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 295#endif 296 297/* 298 * Various low-level settings 299 */ 300#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 301#define CONFIG_SYS_HID0_FINAL HID0_ICE 302 303#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 304#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 305#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 306 307#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 308#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 309 310#define CONFIG_SYS_CS1_START 0xfd000000 311#define CONFIG_SYS_CS1_SIZE 0x00010000 312#define CONFIG_SYS_CS1_CFG 0x10101410 313 314#define CONFIG_SYS_CS3_START 0xfd010000 315#define CONFIG_SYS_CS3_SIZE 0x00010000 316#define CONFIG_SYS_CS3_CFG 0x10109410 317 318#define CONFIG_SYS_CS_BURST 0x00000000 319#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 320 321#define CONFIG_SYS_RESET_ADDRESS 0xff000000 322 323/*----------------------------------------------------------------------- 324 * USB stuff 325 *----------------------------------------------------------------------- 326 */ 327#define CONFIG_USB_CLOCK 0x0001BBBB 328#define CONFIG_USB_CONFIG 0x00001000 329 330/*----------------------------------------------------------------------- 331 * IDE/ATA stuff Supports IDE harddisk 332 *----------------------------------------------------------------------- 333 */ 334 335#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 336 337#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 338#undef CONFIG_IDE_LED /* LED for ide not supported */ 339 340#define CONFIG_IDE_RESET /* reset for ide supported */ 341#define CONFIG_IDE_PREINIT 342 343#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 344#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 345 346#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 347 348#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 349 350/* Offset for data I/O */ 351#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 352 353/* Offset for normal register accesses */ 354#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 355 356/* Offset for alternate registers */ 357#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 358 359/* Interval between registers */ 360#define CONFIG_SYS_ATA_STRIDE 4 361 362/*----------------------------------------------------------------------- 363 * CPLD stuff 364 */ 365#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ 366#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ 367 368/* CPLD program pin configuration */ 369#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ 370#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ 371#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ 372#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ 373 374#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ 375#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ 376#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ 377#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ 378 379#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) 380#define JTAG_GPIO_CFG_SET 0x00000000 381#define JTAG_GPIO_CFG_RESET 0x00F00000 382 383#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) 384#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ 385#define JTAG_GPIO_TMS_EN_RESET 0x00000000 386#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) 387#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ 388#define JTAG_GPIO_TMS_DDR_RESET 0x00000000 389 390#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) 391#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ 392#define JTAG_GPIO_TCK_EN_RESET 0x00000000 393#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) 394#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ 395#define JTAG_GPIO_TCK_DDR_RESET 0x00000000 396 397#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) 398#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ 399#define JTAG_GPIO_TDI_EN_RESET 0x00000000 400#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) 401#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ 402#define JTAG_GPIO_TDI_DDR_RESET 0x00000000 403 404#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) 405#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ 406#define JTAG_GPIO_TDO_EN_RESET 0x00000000 407#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) 408#define JTAG_GPIO_TDO_DDR_SET 0x00000000 409#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ 410 411#endif /* __CONFIG_H */ 412