LXR uboot/include/configs/dlvision.h

   1/*
   2 * (C) Copyright 2009
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  28#define CONFIG_4xx              1       /*  member of PPC4xx family */
  29#define CONFIG_DLVISION         1       /*  on a Neo board */
  30
  31#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  32
  33/*
  34 * Include common defines/options for all AMCC eval boards
  35 */
  36#define CONFIG_HOSTNAME         dlvision
  37#define CONFIG_IDENT_STRING     " dlvision 0.01"
  38#include "amcc-common.h"
  39
  40#define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f */
  41#define CONFIG_MISC_INIT_R              /* call misc_init_r */
  42
  43#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  44
  45/*
  46 * Configure PLL
  47 */
  48#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  49#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  50
  51/* new uImage format support */
  52#define CONFIG_FIT
  53#define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  54
  55#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  56
  57/*
  58 * Default environment variables
  59 */
  60#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  61        CONFIG_AMCC_DEF_ENV                                             \
  62        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  63        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  64        "kernel_addr=fc000000\0"                                        \
  65        "fdt_addr=fc1e0000\0"                                           \
  66        "ramdisk_addr=fc200000\0"                                       \
  67        ""
  68
  69#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  70#define CONFIG_HAS_ETH0
  71#define CONFIG_HAS_ETH1
  72#define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  73#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  74
  75/*
  76 * Commands additional to the ones defined in amcc-common.h
  77 */
  78#define CONFIG_CMD_CACHE
  79#undef CONFIG_CMD_EEPROM
  80
  81/*
  82 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  83 */
  84#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  85
  86/* SDRAM timings used in datasheet */
  87#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  88#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  89#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  90#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  91#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  92
  93/*
  94 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  95 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  96 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  97 * The Linux BASE_BAUD define should match this configuration.
  98 *    baseBaud = cpuClock/(uartDivisor*16)
  99 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 100 * set Linux BASE_BAUD to 403200.
 101 */
 102#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 103#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
 104#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 105#define CONFIG_SYS_BASE_BAUD            691200
 106
 107/*
 108 * I2C stuff
 109 */
 110#define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address*/
 111
 112/*
 113 * FLASH organization
 114 */
 115#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 116#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 117
 118#define CONFIG_SYS_FLASH_BASE           0xFC000000
 119#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 120
 121#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 122#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 123
 124#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 125#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 126
 127#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 128#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protect */
 129
 130#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 131#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 132
 133#ifdef CONFIG_ENV_IS_IN_FLASH
 134#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 135#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 136#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 137
 138/* Address and size of Redundant Environment Sector     */
 139#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 140#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 141#endif
 142
 143/*
 144 * PPC405 GPIO Configuration
 145 */
 146#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 147{ \
 148/* GPIO Core 0 */ \
 149{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 150{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 151{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 152{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 153{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 154{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 155{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 156{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5 */ \
 157{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 158{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 160{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 161{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 164{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 165{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 166{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 167{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 168{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 169{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 170{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 171{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 172{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 173{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 174{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 175{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 176{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 177{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 178{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 179{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 180{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 181} \
 182}
 183
 184/*
 185 * Definitions for initial stack pointer and data area (in data cache)
 186 */
 187/* use on chip memory (OCM) for temperary stack until sdram is tested */
 188#define CONFIG_SYS_TEMP_STACK_OCM        1
 189
 190/* On Chip Memory location */
 191#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 192#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 193#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 194#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
 195
 196#define CONFIG_SYS_GBL_DATA_OFFSET \
 197        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 198#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200/*
 201 * External Bus Controller (EBC) Setup
 202 */
 203
 204/* Memory Bank 0 (NOR-FLASH) initialization */
 205#define CONFIG_SYS_EBC_PB0AP            0x92015480
 206/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 207#define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 208
 209/* Memory Bank 1 (NVRAM) initializatio */
 210#define CONFIG_SYS_EBC_PB1AP            0x92015480
 211/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 212#define CONFIG_SYS_EBC_PB1CR            0xFB858000
 213
 214/* Memory Bank 2 (UART) initialization */
 215#define CONFIG_UART_BASE                0x7f100000
 216#define CONFIG_SYS_EBC_PB2AP            0x92015480
 217/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
 218#define CONFIG_SYS_EBC_PB2CR            0x7f118000
 219
 220/* Memory Bank 3 (Latches) initialization */
 221#define CONFIG_SYS_LATCH_BASE           0x7f200000
 222#define CONFIG_SYS_EBC_PB3AP            0x92015480
 223/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 224#define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 225
 226#endif  /* __CONFIG_H */
 227