1/* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33#include <asm/arch/imx-regs.h> 34 35/* High Level Configuration Options */ 36#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ 37#define CONFIG_MX31 /* in a mx31 */ 38#define CONFIG_MX31_HCLK_FREQ 26000000 39#define CONFIG_MX31_CLK32 32768 40 41#define CONFIG_DISPLAY_CPUINFO 42#define CONFIG_DISPLAY_BOARDINFO 43 44#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 45#define CONFIG_SETUP_MEMORY_TAGS 46#define CONFIG_INITRD_TAG 47 48#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 49#define CONFIG_SKIP_LOWLEVEL_INIT 50#endif 51 52/* 53 * Size of malloc() pool 54 */ 55#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 56 57/* 58 * Hardware drivers 59 */ 60 61#define CONFIG_MXC_UART 62#define CONFIG_SYS_MX31_UART1 63#define CONFIG_HW_WATCHDOG 64#define CONFIG_MXC_GPIO 65 66#define CONFIG_HARD_SPI 67#define CONFIG_MXC_SPI 68#define CONFIG_DEFAULT_SPI_BUS 1 69#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 70 71#define CONFIG_FSL_PMIC 72#define CONFIG_FSL_PMIC_BUS 1 73#define CONFIG_FSL_PMIC_CS 2 74#define CONFIG_FSL_PMIC_CLK 1000000 75#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 76#define CONFIG_RTC_MC13783 77 78/* allow to overwrite serial and ethaddr */ 79#define CONFIG_ENV_OVERWRITE 80#define CONFIG_CONS_INDEX 1 81#define CONFIG_BAUDRATE 115200 82#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 83 84/*********************************************************** 85 * Command definition 86 ***********************************************************/ 87 88#include <config_cmd_default.h> 89 90#define CONFIG_CMD_MII 91#define CONFIG_CMD_PING 92#define CONFIG_CMD_DHCP 93#define CONFIG_CMD_SPI 94#define CONFIG_CMD_DATE 95#define CONFIG_CMD_NAND 96 97/* 98 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 99 * that CFG_NO_FLASH is undefined). 100 */ 101#undef CONFIG_CMD_IMLS 102 103#define BOARD_LATE_INIT 104 105#define CONFIG_BOOTDELAY 3 106 107#define CONFIG_EXTRA_ENV_SETTINGS \ 108 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 109 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 110 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 111 "bootcmd=run bootcmd_net\0" \ 112 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 113 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 114 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ 115 "nand erase 0x0 0x40000; " \ 116 "nand write 0x81000000 0x0 0x40000\0" 117 118#define CONFIG_NET_MULTI 119#define CONFIG_SMC911X 120#define CONFIG_SMC911X_BASE 0xB6000000 121#define CONFIG_SMC911X_32_BIT 122 123/* 124 * Miscellaneous configurable options 125 */ 126#define CONFIG_SYS_LONGHELP /* undef to save memory */ 127#define CONFIG_SYS_PROMPT "uboot> " 128#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 129/* Print Buffer Size */ 130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 131 sizeof(CONFIG_SYS_PROMPT)+16) 132/* max number of command args */ 133#define CONFIG_SYS_MAXARGS 16 134/* Boot Argument Buffer Size */ 135#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 136 137/* memtest works on */ 138#define CONFIG_SYS_MEMTEST_START 0x80000000 139#define CONFIG_SYS_MEMTEST_END 0x10000 140 141/* default load address */ 142#define CONFIG_SYS_LOAD_ADDR 0x81000000 143 144#define CONFIG_SYS_HZ 1000 145 146#define CONFIG_CMDLINE_EDITING 147 148/*----------------------------------------------------------------------- 149 * Stack sizes 150 * 151 * The stack sizes are set up in start.S using the settings below 152 */ 153#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 154 155/*----------------------------------------------------------------------- 156 * Physical Memory Map 157 */ 158#define CONFIG_NR_DRAM_BANKS 1 159#define PHYS_SDRAM_1 CSD0_BASE 160#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 161#define CONFIG_BOARD_EARLY_INIT_F 162 163#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 164#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 165#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 166#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 167 GENERATED_GBL_DATA_SIZE) 168#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 169 CONFIG_SYS_GBL_DATA_OFFSET) 170 171/*----------------------------------------------------------------------- 172 * FLASH and environment organization 173 */ 174/* No NOR flash present */ 175#define CONFIG_SYS_NO_FLASH 176 177#define CONFIG_ENV_IS_IN_NAND 178#define CONFIG_ENV_OFFSET 0x40000 179#define CONFIG_ENV_OFFSET_REDUND 0x60000 180#define CONFIG_ENV_SIZE (128 * 1024) 181 182/* 183 * NAND driver 184 */ 185#define CONFIG_NAND_MXC 186#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 187#define CONFIG_SYS_MAX_NAND_DEVICE 1 188#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 189#define CONFIG_MXC_NAND_HWECC 190#define CONFIG_SYS_NAND_LARGEPAGE 191 192/* NAND configuration for the NAND_SPL */ 193 194/* Start copying real U-boot from the second page */ 195#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 196#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 197/* Load U-Boot to this address */ 198#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 199#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 200 201#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 202#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 203#define CONFIG_SYS_NAND_PAGE_COUNT 64 204#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 205#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 206 207 208/* Configuration of lowlevel_init.S (clocks and SDRAM) */ 209#define CCM_CCMR_SETUP 0x074B0BF5 210#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ 211 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ 212 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ 213 PDR0_MCU_PODF(0)) 214#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 215 PLL_MFN(12)) 216 217#define ESDMISC_MDDR_SETUP 0x00000004 218#define ESDMISC_MDDR_RESET_DL 0x0000000c 219#define ESDCFG0_MDDR_SETUP 0x006ac73a 220 221#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 222#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 223 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 224#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 225#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 226#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 227#define ESDCTL_RW ESDCTL_SETTINGS 228 229#endif /* __CONFIG_H */ 230