1/* 2 * (C) Copyright 2011 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Lei Wen <leiwen@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25/* 26 * This file should be included in board config header file. 27 * 28 * It supports common definitions for Kirkwood platform 29 */ 30 31#ifndef _KW_CONFIG_H 32#define _KW_CONFIG_H 33 34#if defined (CONFIG_KW88F6281) 35#include <asm/arch/kw88f6281.h> 36#elif defined (CONFIG_KW88F6192) 37#include <asm/arch/kw88f6192.h> 38#else 39#error "SOC Name not defined" 40#endif /* CONFIG_KW88F6281 */ 41 42#include <asm/arch/kirkwood.h> 43#define CONFIG_ARM926EJS 1 /* Basic Architecture */ 44#define CONFIG_SYS_CACHELINE_SIZE 32 45 /* default Dcache Line length for kirkwood */ 46#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ 47#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 48#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 49#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 50 51/* 52 * By default kwbimage.cfg from board specific folder is used 53 * If for some board, different configuration file need to be used, 54 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file 55 */ 56#ifndef CONFIG_SYS_KWD_CONFIG 57#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg 58#endif /* CONFIG_SYS_KWD_CONFIG */ 59 60/* Kirkwood has 2k of Security SRAM, use it for SP */ 61#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 62#define CONFIG_NR_DRAM_BANKS_MAX 2 63 64#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE 65#define MV_UART_CONSOLE_BASE KW_UART0_BASE 66#define MV_SATA_BASE KW_SATA_BASE 67#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 68#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 69 70/* 71 * NAND configuration 72 */ 73#ifdef CONFIG_CMD_NAND 74#define CONFIG_NAND_KIRKWOOD 75#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 76#define NAND_ALLOW_ERASE_ALL 1 77#endif 78 79/* 80 * SPI Flash configuration 81 */ 82#ifdef CONFIG_CMD_SF 83#define CONFIG_HARD_SPI 1 84#define CONFIG_KIRKWOOD_SPI 1 85#define CONFIG_ENV_SPI_BUS 0 86#define CONFIG_ENV_SPI_CS 0 87#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ 88#endif 89 90/* 91 * Ethernet Driver configuration 92 */ 93#ifdef CONFIG_CMD_NET 94#define CONFIG_CMD_MII 95#define CONFIG_NETCONSOLE /* include NetConsole support */ 96#define CONFIG_MII /* expose smi ove miiphy interface */ 97#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ 98#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 99#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 100#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 101#endif /* CONFIG_CMD_NET */ 102 103/* 104 * USB/EHCI 105 */ 106#ifdef CONFIG_CMD_USB 107#define CONFIG_USB_EHCI_KIRKWOOD 108#define CONFIG_EHCI_IS_TDI 109#endif /* CONFIG_CMD_USB */ 110 111/* 112 * IDE Support on SATA ports 113 */ 114#ifdef CONFIG_CMD_IDE 115#define __io 116#define CONFIG_CMD_EXT2 117#define CONFIG_MVSATA_IDE 118#define CONFIG_IDE_PREINIT 119#define CONFIG_MVSATA_IDE_USE_PORT1 120/* Needs byte-swapping for ATA data register */ 121#define CONFIG_IDE_SWAP_IO 122/* Data, registers and alternate blocks are at the same offset */ 123#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 124#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 125#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 126/* Each 8-bit ATA register is aligned to a 4-bytes address */ 127#define CONFIG_SYS_ATA_STRIDE 4 128/* Controller supports 48-bits LBA addressing */ 129#define CONFIG_LBA48 130/* CONFIG_CMD_IDE requires some #defines for ATA registers */ 131#define CONFIG_SYS_IDE_MAXBUS 2 132#define CONFIG_SYS_IDE_MAXDEVICE 2 133/* ATA registers base is at SATA controller base */ 134#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 135#endif /* CONFIG_CMD_IDE */ 136 137/* 138 * I2C related stuff 139 */ 140#ifdef CONFIG_CMD_I2C 141#ifndef CONFIG_SOFT_I2C 142#define CONFIG_I2C_MVTWSI 143#endif 144#define CONFIG_SYS_I2C_SLAVE 0x0 145#define CONFIG_SYS_I2C_SPEED 100000 146#endif 147 148#endif /* _KW_CONFIG_H */ 149