LXR uboot/arch/powerpc/cpu/mpc8xx/fec.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <malloc.h>
  26#include <commproc.h>
  27#include <net.h>
  28#include <command.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32#undef  ET_DEBUG
  33
  34#if defined(CONFIG_CMD_NET) && \
  35        (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
  36
  37/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
  38#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
  39#define CONFIG_ETHER_ON_FEC1 1
  40#endif
  41
  42/* define WANT_MII when MII support is required */
  43#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
  44#define WANT_MII
  45#else
  46#undef WANT_MII
  47#endif
  48
  49#if defined(WANT_MII)
  50#include <miiphy.h>
  51
  52#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  53#error "CONFIG_MII has to be defined!"
  54#endif
  55
  56#endif
  57
  58#if defined(CONFIG_RMII) && !defined(WANT_MII)
  59#error RMII support is unusable without a working PHY.
  60#endif
  61
  62#ifdef CONFIG_SYS_DISCOVER_PHY
  63static int mii_discover_phy(struct eth_device *dev);
  64#endif
  65
  66int fec8xx_miiphy_read(const char *devname, unsigned char addr,
  67                unsigned char  reg, unsigned short *value);
  68int fec8xx_miiphy_write(const char *devname, unsigned char  addr,
  69                unsigned char  reg, unsigned short value);
  70
  71static struct ether_fcc_info_s
  72{
  73        int ether_index;
  74        int fecp_offset;
  75        int phy_addr;
  76        int actual_phy_addr;
  77        int initialized;
  78}
  79        ether_fcc_info[] = {
  80#if defined(CONFIG_ETHER_ON_FEC1)
  81        {
  82                0,
  83                offsetof(immap_t, im_cpm.cp_fec1),
  84#if defined(CONFIG_FEC1_PHY)
  85                CONFIG_FEC1_PHY,
  86#else
  87                -1,     /* discover */
  88#endif
  89                -1,
  90                0,
  91
  92        },
  93#endif
  94#if defined(CONFIG_ETHER_ON_FEC2)
  95        {
  96                1,
  97                offsetof(immap_t, im_cpm.cp_fec2),
  98#if defined(CONFIG_FEC2_PHY)
  99                CONFIG_FEC2_PHY,
 100#else
 101                -1,
 102#endif
 103                -1,
 104                0,
 105        },
 106#endif
 107};
 108
 109/* Ethernet Transmit and Receive Buffers */
 110#define DBUF_LENGTH  1520
 111
 112#define TX_BUF_CNT 2
 113
 114#define TOUT_LOOP 100
 115
 116#define PKT_MAXBUF_SIZE         1518
 117#define PKT_MINBUF_SIZE         64
 118#define PKT_MAXBLR_SIZE         1520
 119
 120#ifdef __GNUC__
 121static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
 122#else
 123#error txbuf must be aligned.
 124#endif
 125
 126static uint rxIdx;      /* index of the current RX buffer */
 127static uint txIdx;      /* index of the current TX buffer */
 128
 129/*
 130  * FEC Ethernet Tx and Rx buffer descriptors allocated at the
 131  *  immr->udata_bd address on Dual-Port RAM
 132  * Provide for Double Buffering
 133  */
 134
 135typedef volatile struct CommonBufferDescriptor {
 136    cbd_t rxbd[PKTBUFSRX];              /* Rx BD */
 137    cbd_t txbd[TX_BUF_CNT];             /* Tx BD */
 138} RTXBD;
 139
 140static RTXBD *rtx = NULL;
 141
 142static int fec_send(struct eth_device* dev, volatile void *packet, int length);
 143static int fec_recv(struct eth_device* dev);
 144static int fec_init(struct eth_device* dev, bd_t * bd);
 145static void fec_halt(struct eth_device* dev);
 146#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 147static void __mii_init(void);
 148#endif
 149
 150int fec_initialize(bd_t *bis)
 151{
 152        struct eth_device* dev;
 153        struct ether_fcc_info_s *efis;
 154        int             i;
 155
 156        for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
 157
 158                dev = malloc(sizeof(*dev));
 159                if (dev == NULL)
 160                        hang();
 161
 162                memset(dev, 0, sizeof(*dev));
 163
 164                /* for FEC1 make sure that the name of the interface is the same
 165                   as the old one for compatibility reasons */
 166                if (i == 0) {
 167                        sprintf (dev->name, "FEC");
 168                } else {
 169                        sprintf (dev->name, "FEC%d",
 170                                ether_fcc_info[i].ether_index + 1);
 171                }
 172
 173                efis = &ether_fcc_info[i];
 174
 175                /*
 176                 * reset actual phy addr
 177                 */
 178                efis->actual_phy_addr = -1;
 179
 180                dev->priv = efis;
 181                dev->init = fec_init;
 182                dev->halt = fec_halt;
 183                dev->send = fec_send;
 184                dev->recv = fec_recv;
 185
 186                eth_register(dev);
 187
 188#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 189                miiphy_register(dev->name,
 190                        fec8xx_miiphy_read, fec8xx_miiphy_write);
 191#endif
 192        }
 193        return 1;
 194}
 195
 196static int fec_send(struct eth_device* dev, volatile void *packet, int length)
 197{
 198        int j, rc;
 199        struct ether_fcc_info_s *efis = dev->priv;
 200        volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 201
 202        /* section 16.9.23.3
 203         * Wait for ready
 204         */
 205        j = 0;
 206        while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
 207                udelay(1);
 208                j++;
 209        }
 210        if (j>=TOUT_LOOP) {
 211                printf("TX not ready\n");
 212        }
 213
 214        rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
 215        rtx->txbd[txIdx].cbd_datlen  = length;
 216        rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
 217        __asm__ ("eieio");
 218
 219        /* Activate transmit Buffer Descriptor polling */
 220        fecp->fec_x_des_active = 0x01000000;    /* Descriptor polling active    */
 221
 222        j = 0;
 223        while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
 224#if defined(CONFIG_ICU862)
 225                udelay(10);
 226#else
 227                udelay(1);
 228#endif
 229                j++;
 230        }
 231        if (j>=TOUT_LOOP) {
 232                printf("TX timeout\n");
 233        }
 234#ifdef ET_DEBUG
 235        printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
 236        __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
 237        (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
 238#endif
 239        /* return only status bits */;
 240        rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
 241
 242        txIdx = (txIdx + 1) % TX_BUF_CNT;
 243
 244        return rc;
 245}
 246
 247static int fec_recv (struct eth_device *dev)
 248{
 249        struct ether_fcc_info_s *efis = dev->priv;
 250        volatile fec_t *fecp =
 251                (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
 252        int length;
 253
 254        for (;;) {
 255                /* section 16.9.23.2 */
 256                if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
 257                        length = -1;
 258                        break;  /* nothing received - leave for() loop */
 259                }
 260
 261                length = rtx->rxbd[rxIdx].cbd_datlen;
 262
 263                if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
 264#ifdef ET_DEBUG
 265                        printf ("%s[%d] err: %x\n",
 266                                __FUNCTION__, __LINE__,
 267                                rtx->rxbd[rxIdx].cbd_sc);
 268#endif
 269                } else {
 270                        volatile uchar *rx = NetRxPackets[rxIdx];
 271
 272                        length -= 4;
 273
 274#if defined(CONFIG_CMD_CDP)
 275                        if ((rx[0] & 1) != 0
 276                            && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
 277                            && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
 278                                rx = NULL;
 279#endif
 280                        /*
 281                         * Pass the packet up to the protocol layers.
 282                         */
 283                        if (rx != NULL)
 284                                NetReceive (rx, length);
 285                }
 286
 287                /* Give the buffer back to the FEC. */
 288                rtx->rxbd[rxIdx].cbd_datlen = 0;
 289
 290                /* wrap around buffer index when necessary */
 291                if ((rxIdx + 1) >= PKTBUFSRX) {
 292                        rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
 293                                (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 294                        rxIdx = 0;
 295                } else {
 296                        rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
 297                        rxIdx++;
 298                }
 299
 300                __asm__ ("eieio");
 301
 302                /* Try to fill Buffer Descriptors */
 303                fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 304        }
 305
 306        return length;
 307}
 308
 309/**************************************************************
 310 *
 311 * FEC Ethernet Initialization Routine
 312 *
 313 *************************************************************/
 314
 315#define FEC_ECNTRL_PINMUX       0x00000004
 316#define FEC_ECNTRL_ETHER_EN     0x00000002
 317#define FEC_ECNTRL_RESET        0x00000001
 318
 319#define FEC_RCNTRL_BC_REJ       0x00000010
 320#define FEC_RCNTRL_PROM         0x00000008
 321#define FEC_RCNTRL_MII_MODE     0x00000004
 322#define FEC_RCNTRL_DRT          0x00000002
 323#define FEC_RCNTRL_LOOP         0x00000001
 324
 325#define FEC_TCNTRL_FDEN         0x00000004
 326#define FEC_TCNTRL_HBC          0x00000002
 327#define FEC_TCNTRL_GTS          0x00000001
 328
 329#define FEC_RESET_DELAY         50
 330
 331#if defined(CONFIG_RMII)
 332
 333static inline void fec_10Mbps(struct eth_device *dev)
 334{
 335        struct ether_fcc_info_s *efis = dev->priv;
 336        int fecidx = efis->ether_index;
 337        uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
 338
 339        if ((unsigned int)fecidx >= 2)
 340                hang();
 341
 342        ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |=  mask;
 343}
 344
 345static inline void fec_100Mbps(struct eth_device *dev)
 346{
 347        struct ether_fcc_info_s *efis = dev->priv;
 348        int fecidx = efis->ether_index;
 349        uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
 350
 351        if ((unsigned int)fecidx >= 2)
 352                hang();
 353
 354        ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
 355}
 356
 357#endif
 358
 359static inline void fec_full_duplex(struct eth_device *dev)
 360{
 361        struct ether_fcc_info_s *efis = dev->priv;
 362        volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 363
 364        fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
 365        fecp->fec_x_cntrl |=  FEC_TCNTRL_FDEN;  /* FD enable */
 366}
 367
 368static inline void fec_half_duplex(struct eth_device *dev)
 369{
 370        struct ether_fcc_info_s *efis = dev->priv;
 371        volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 372
 373        fecp->fec_r_cntrl |=  FEC_RCNTRL_DRT;
 374        fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN;  /* FD disable */
 375}
 376
 377static void fec_pin_init(int fecidx)
 378{
 379        bd_t           *bd = gd->bd;
 380        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 381
 382        /*
 383         * Set MII speed to 2.5 MHz or slightly below.
 384         *
 385         * According to the MPC860T (Rev. D) Fast ethernet controller user
 386         * manual (6.2.14),
 387         * the MII management interface clock must be less than or equal
 388         * to 2.5 MHz.
 389         * This MDC frequency is equal to system clock / (2 * MII_SPEED).
 390         * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
 391         *
 392         * All MII configuration is done via FEC1 registers:
 393         */
 394        immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
 395
 396#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
 397        {
 398                volatile fec_t *fecp;
 399
 400                /*
 401                 * only two FECs please
 402                 */
 403                if ((unsigned int)fecidx >= 2)
 404                        hang();
 405
 406                if (fecidx == 0)
 407                        fecp = &immr->im_cpm.cp_fec1;
 408                else
 409                        fecp = &immr->im_cpm.cp_fec2;
 410
 411                /* our PHYs are the limit at 2.5 MHz */
 412                fecp->fec_mii_speed <<= 1;
 413        }
 414#endif
 415
 416#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
 417        /* use MDC for MII */
 418        immr->im_ioport.iop_pdpar |=  0x0080;
 419        immr->im_ioport.iop_pddir &= ~0x0080;
 420#endif
 421
 422        if (fecidx == 0) {
 423#if defined(CONFIG_ETHER_ON_FEC1)
 424
 425#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
 426
 427#if !defined(CONFIG_RMII)
 428
 429                immr->im_ioport.iop_papar |=  0xf830;
 430                immr->im_ioport.iop_padir |=  0x0830;
 431                immr->im_ioport.iop_padir &= ~0xf000;
 432
 433                immr->im_cpm.cp_pbpar     |=  0x00001001;
 434                immr->im_cpm.cp_pbdir     &= ~0x00001001;
 435
 436                immr->im_ioport.iop_pcpar |=  0x000c;
 437                immr->im_ioport.iop_pcdir &= ~0x000c;
 438
 439                immr->im_cpm.cp_pepar     |=  0x00000003;
 440                immr->im_cpm.cp_pedir     |=  0x00000003;
 441                immr->im_cpm.cp_peso      &= ~0x00000003;
 442
 443                immr->im_cpm.cp_cptr      &= ~0x00000100;
 444
 445#else
 446
 447#if !defined(CONFIG_FEC1_PHY_NORXERR)
 448                immr->im_ioport.iop_papar |=  0x1000;
 449                immr->im_ioport.iop_padir &= ~0x1000;
 450#endif
 451                immr->im_ioport.iop_papar |=  0xe810;
 452                immr->im_ioport.iop_padir |=  0x0810;
 453                immr->im_ioport.iop_padir &= ~0xe000;
 454
 455                immr->im_cpm.cp_pbpar     |=  0x00000001;
 456                immr->im_cpm.cp_pbdir     &= ~0x00000001;
 457
 458                immr->im_cpm.cp_cptr      |=  0x00000100;
 459                immr->im_cpm.cp_cptr      &= ~0x00000050;
 460
 461#endif /* !CONFIG_RMII */
 462
 463#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
 464                /*
 465                 * Configure all of port D for MII.
 466                 */
 467                immr->im_ioport.iop_pdpar = 0x1fff;
 468
 469                /*
 470                 * Bits moved from Rev. D onward
 471                 */
 472                if ((get_immr(0) & 0xffff) < 0x0501)
 473                        immr->im_ioport.iop_pddir = 0x1c58;     /* Pre rev. D */
 474                else
 475                        immr->im_ioport.iop_pddir = 0x1fff;     /* Rev. D and later */
 476#else
 477                /*
 478                 * Configure port A for MII.
 479                 */
 480
 481#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
 482
 483                /*
 484                 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
 485                 * * of CPU, so for this board we need to configure Utopia and
 486                 * * enable PD8 to MII-MDC function
 487                 */
 488                immr->im_ioport.iop_pdpar |= 0x4080;
 489#endif
 490
 491                /*
 492                 * Has Utopia been configured?
 493                 */
 494                if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
 495                        /*
 496                         * YES - Use MUXED mode for UTOPIA bus.
 497                         * This frees Port A for use by MII (see 862UM table 41-6).
 498                         */
 499                        immr->im_ioport.utmode &= ~0x80;
 500                } else {
 501                        /*
 502                         * NO - set SPLIT mode for UTOPIA bus.
 503                         *
 504                         * This doesn't really effect UTOPIA (which isn't
 505                         * enabled anyway) but just tells the 862
 506                         * to use port A for MII (see 862UM table 41-6).
 507                         */
 508                        immr->im_ioport.utmode |= 0x80;
 509                }
 510#endif                          /* !defined(CONFIG_ICU862) */
 511
 512#endif  /* CONFIG_ETHER_ON_FEC1 */
 513        } else if (fecidx == 1) {
 514
 515#if defined(CONFIG_ETHER_ON_FEC2)
 516
 517#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
 518
 519#if !defined(CONFIG_RMII)
 520                immr->im_cpm.cp_pepar     |=  0x0003fffc;
 521                immr->im_cpm.cp_pedir     |=  0x0003fffc;
 522                immr->im_cpm.cp_peso      &= ~0x000087fc;
 523                immr->im_cpm.cp_peso      |=  0x00037800;
 524
 525                immr->im_cpm.cp_cptr      &= ~0x00000080;
 526#else
 527
 528#if !defined(CONFIG_FEC2_PHY_NORXERR)
 529                immr->im_cpm.cp_pepar     |=  0x00000010;
 530                immr->im_cpm.cp_pedir     |=  0x00000010;
 531                immr->im_cpm.cp_peso      &= ~0x00000010;
 532#endif
 533                immr->im_cpm.cp_pepar     |=  0x00039620;
 534                immr->im_cpm.cp_pedir     |=  0x00039620;
 535                immr->im_cpm.cp_peso      |=  0x00031000;
 536                immr->im_cpm.cp_peso      &= ~0x00008620;
 537
 538                immr->im_cpm.cp_cptr      |=  0x00000080;
 539                immr->im_cpm.cp_cptr      &= ~0x00000028;
 540#endif /* CONFIG_RMII */
 541
 542#endif /* CONFIG_MPC885_FAMILY */
 543
 544#endif /* CONFIG_ETHER_ON_FEC2 */
 545
 546        }
 547}
 548
 549static int fec_reset(volatile fec_t *fecp)
 550{
 551        int i;
 552
 553        /* Whack a reset.
 554         * A delay is required between a reset of the FEC block and
 555         * initialization of other FEC registers because the reset takes
 556         * some time to complete. If you don't delay, subsequent writes
 557         * to FEC registers might get killed by the reset routine which is
 558         * still in progress.
 559         */
 560
 561        fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
 562        for (i = 0;
 563             (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 564             ++i) {
 565                udelay (1);
 566        }
 567        if (i == FEC_RESET_DELAY)
 568                return -1;
 569
 570        return 0;
 571}
 572
 573static int fec_init (struct eth_device *dev, bd_t * bd)
 574{
 575        struct ether_fcc_info_s *efis = dev->priv;
 576        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 577        volatile fec_t *fecp =
 578                (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
 579        int i;
 580
 581        if (efis->ether_index == 0) {
 582#if defined(CONFIG_FADS)        /* FADS family uses FPGA (BCSR) to control PHYs */
 583#if defined(CONFIG_MPC885ADS)
 584                *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
 585#else
 586                /* configure FADS for fast (FEC) ethernet, half-duplex */
 587                /* The LXT970 needs about 50ms to recover from reset, so
 588                 * wait for it by discovering the PHY before leaving eth_init().
 589                 */
 590                {
 591                        volatile uint *bcsr4 = (volatile uint *) BCSR4;
 592
 593                        *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
 594                                | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
 595                                   BCSR4_FETHRST);
 596
 597                        /* reset the LXT970 PHY */
 598                        *bcsr4 &= ~BCSR4_FETHRST;
 599                        udelay (10);
 600                        *bcsr4 |= BCSR4_FETHRST;
 601                        udelay (10);
 602                }
 603#endif /* CONFIG_MPC885ADS */
 604#endif /* CONFIG_FADS */
 605        }
 606
 607#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 608        /* the MII interface is connected to FEC1
 609         * so for the miiphy_xxx function to work we must
 610         * call mii_init since fec_halt messes the thing up
 611         */
 612        if (efis->ether_index != 0)
 613                __mii_init();
 614#endif
 615
 616        if (fec_reset(fecp) < 0)
 617                printf ("FEC_RESET_DELAY timeout\n");
 618
 619        /* We use strictly polling mode only
 620         */
 621        fecp->fec_imask = 0;
 622
 623        /* Clear any pending interrupt
 624         */
 625        fecp->fec_ievent = 0xffc0;
 626
 627        /* No need to set the IVEC register */
 628
 629        /* Set station address
 630         */
 631#define ea dev->enetaddr
 632        fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
 633        fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
 634#undef ea
 635
 636#if defined(CONFIG_CMD_CDP)
 637        /*
 638         * Turn on multicast address hash table
 639         */
 640        fecp->fec_hash_table_high = 0xffffffff;
 641        fecp->fec_hash_table_low = 0xffffffff;
 642#else
 643        /* Clear multicast address hash table
 644         */
 645        fecp->fec_hash_table_high = 0;
 646        fecp->fec_hash_table_low = 0;
 647#endif
 648
 649        /* Set maximum receive buffer size.
 650         */
 651        fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
 652
 653        /* Set maximum frame length
 654         */
 655        fecp->fec_r_hash = PKT_MAXBUF_SIZE;
 656
 657        /*
 658         * Setup Buffers and Buffer Desriptors
 659         */
 660        rxIdx = 0;
 661        txIdx = 0;
 662
 663        if (!rtx) {
 664#ifdef CONFIG_SYS_ALLOC_DPRAM
 665                rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
 666                                 dpram_alloc_align (sizeof (RTXBD), 8));
 667#else
 668                rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
 669#endif
 670        }
 671        /*
 672         * Setup Receiver Buffer Descriptors (13.14.24.18)
 673         * Settings:
 674         *     Empty, Wrap
 675         */
 676        for (i = 0; i < PKTBUFSRX; i++) {
 677                rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 678                rtx->rxbd[i].cbd_datlen = 0;    /* Reset */
 679                rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
 680        }
 681        rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 682
 683        /*
 684         * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 685         * Settings:
 686         *    Last, Tx CRC
 687         */
 688        for (i = 0; i < TX_BUF_CNT; i++) {
 689                rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
 690                rtx->txbd[i].cbd_datlen = 0;    /* Reset */
 691                rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 692        }
 693        rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 694
 695        /* Set receive and transmit descriptor base
 696         */
 697        fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
 698        fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
 699
 700        /* Enable MII mode
 701         */
 702#if 0                           /* Full duplex mode */
 703        fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
 704        fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
 705#else  /* Half duplex mode */
 706        fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
 707        fecp->fec_x_cntrl = 0;
 708#endif
 709
 710        /* Enable big endian and don't care about SDMA FC.
 711         */
 712        fecp->fec_fun_code = 0x78000000;
 713
 714        /*
 715         * Setup the pin configuration of the FEC
 716         */
 717        fec_pin_init (efis->ether_index);
 718
 719        rxIdx = 0;
 720        txIdx = 0;
 721
 722        /*
 723         * Now enable the transmit and receive processing
 724         */
 725        fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
 726
 727        if (efis->phy_addr == -1) {
 728#ifdef CONFIG_SYS_DISCOVER_PHY
 729                /*
 730                 * wait for the PHY to wake up after reset
 731                 */
 732                efis->actual_phy_addr = mii_discover_phy (dev);
 733
 734                if (efis->actual_phy_addr == -1) {
 735                        printf ("Unable to discover phy!\n");
 736                        return -1;
 737                }
 738#else
 739                efis->actual_phy_addr = -1;
 740#endif
 741        } else {
 742                efis->actual_phy_addr = efis->phy_addr;
 743        }
 744
 745#if defined(CONFIG_MII) && defined(CONFIG_RMII)
 746        /*
 747         * adapt the RMII speed to the speed of the phy
 748         */
 749        if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
 750                fec_100Mbps (dev);
 751        } else {
 752                fec_10Mbps (dev);
 753        }
 754#endif
 755
 756#if defined(CONFIG_MII)
 757        /*
 758         * adapt to the half/full speed settings
 759         */
 760        if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
 761                fec_full_duplex (dev);
 762        } else {
 763                fec_half_duplex (dev);
 764        }
 765#endif
 766
 767        /* And last, try to fill Rx Buffer Descriptors */
 768        fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 769
 770        efis->initialized = 1;
 771
 772        return 0;
 773}
 774
 775
 776static void fec_halt(struct eth_device* dev)
 777{
 778        struct ether_fcc_info_s *efis = dev->priv;
 779        volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
 780        int i;
 781
 782        /* avoid halt if initialized; mii gets stuck otherwise */
 783        if (!efis->initialized)
 784                return;
 785
 786        /* Whack a reset.
 787         * A delay is required between a reset of the FEC block and
 788         * initialization of other FEC registers because the reset takes
 789         * some time to complete. If you don't delay, subsequent writes
 790         * to FEC registers might get killed by the reset routine which is
 791         * still in progress.
 792         */
 793
 794        fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
 795        for (i = 0;
 796             (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 797             ++i) {
 798                udelay (1);
 799        }
 800        if (i == FEC_RESET_DELAY) {
 801                printf ("FEC_RESET_DELAY timeout\n");
 802                return;
 803        }
 804
 805        efis->initialized = 0;
 806}
 807
 808#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 809
 810/* Make MII read/write commands for the FEC.
 811*/
 812
 813#define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | \
 814                                                (REG & 0x1f) << 18))
 815
 816#define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | \
 817                                                (REG & 0x1f) << 18) | \
 818                                                (VAL & 0xffff))
 819
 820/* Interrupt events/masks.
 821*/
 822#define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
 823#define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
 824#define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
 825#define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
 826#define FEC_ENET_TXF    ((uint)0x08000000)      /* Full frame transmitted */
 827#define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
 828#define FEC_ENET_RXF    ((uint)0x02000000)      /* Full frame received */
 829#define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
 830#define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
 831#define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
 832
 833/* PHY identification
 834 */
 835#define PHY_ID_LXT970           0x78100000      /* LXT970 */
 836#define PHY_ID_LXT971           0x001378e0      /* LXT971 and 972 */
 837#define PHY_ID_82555            0x02a80150      /* Intel 82555 */
 838#define PHY_ID_QS6612           0x01814400      /* QS6612 */
 839#define PHY_ID_AMD79C784        0x00225610      /* AMD 79C784 */
 840#define PHY_ID_LSI80225         0x0016f870      /* LSI 80225 */
 841#define PHY_ID_LSI80225B        0x0016f880      /* LSI 80225/B */
 842#define PHY_ID_DM9161           0x0181B880      /* Davicom DM9161 */
 843#define PHY_ID_KSM8995M         0x00221450      /* MICREL KS8995MA */
 844
 845/* send command to phy using mii, wait for result */
 846static uint
 847mii_send(uint mii_cmd)
 848{
 849        uint mii_reply;
 850        volatile fec_t  *ep;
 851        int cnt;
 852
 853        ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
 854
 855        ep->fec_mii_data = mii_cmd;     /* command to phy */
 856
 857        /* wait for mii complete */
 858        cnt = 0;
 859        while (!(ep->fec_ievent & FEC_ENET_MII)) {
 860                if (++cnt > 1000) {
 861                        printf("mii_send STUCK!\n");
 862                        break;
 863                }
 864        }
 865        mii_reply = ep->fec_mii_data;           /* result from phy */
 866        ep->fec_ievent = FEC_ENET_MII;          /* clear MII complete */
 867#if 0
 868        printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
 869                __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
 870#endif
 871        return (mii_reply & 0xffff);            /* data read from phy */
 872}
 873#endif
 874
 875#if defined(CONFIG_SYS_DISCOVER_PHY)
 876static int mii_discover_phy(struct eth_device *dev)
 877{
 878#define MAX_PHY_PASSES 11
 879        uint phyno;
 880        int  pass;
 881        uint phytype;
 882        int phyaddr;
 883
 884        phyaddr = -1;   /* didn't find a PHY yet */
 885        for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 886                if (pass > 1) {
 887                        /* PHY may need more time to recover from reset.
 888                         * The LXT970 needs 50ms typical, no maximum is
 889                         * specified, so wait 10ms before try again.
 890                         * With 11 passes this gives it 100ms to wake up.
 891                         */
 892                        udelay(10000);  /* wait 10ms */
 893                }
 894                for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
 895                        phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
 896#ifdef ET_DEBUG
 897                        printf("PHY type 0x%x pass %d type ", phytype, pass);
 898#endif
 899                        if (phytype != 0xffff) {
 900                                phyaddr = phyno;
 901                                phytype |= mii_send(mk_mii_read(phyno,
 902                                                                MII_PHYSID1)) << 16;
 903
 904#ifdef ET_DEBUG
 905                                printf("PHY @ 0x%x pass %d type ",phyno,pass);
 906                                switch (phytype & 0xfffffff0) {
 907                                case PHY_ID_LXT970:
 908                                        printf("LXT970\n");
 909                                        break;
 910                                case PHY_ID_LXT971:
 911                                        printf("LXT971\n");
 912                                        break;
 913                                case PHY_ID_82555:
 914                                        printf("82555\n");
 915                                        break;
 916                                case PHY_ID_QS6612:
 917                                        printf("QS6612\n");
 918                                        break;
 919                                case PHY_ID_AMD79C784:
 920                                        printf("AMD79C784\n");
 921                                        break;
 922                                case PHY_ID_LSI80225B:
 923                                        printf("LSI L80225/B\n");
 924                                        break;
 925                                case PHY_ID_DM9161:
 926                                        printf("Davicom DM9161\n");
 927                                        break;
 928                                case PHY_ID_KSM8995M:
 929                                        printf("MICREL KS8995M\n");
 930                                        break;
 931                                default:
 932                                        printf("0x%08x\n", phytype);
 933                                        break;
 934                                }
 935#endif
 936                        }
 937                }
 938        }
 939        if (phyaddr < 0) {
 940                printf("No PHY device found.\n");
 941        }
 942        return phyaddr;
 943}
 944#endif  /* CONFIG_SYS_DISCOVER_PHY */
 945
 946#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
 947
 948/****************************************************************************
 949 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
 950 * This function is a subset of eth_init
 951 ****************************************************************************
 952 */
 953static void __mii_init(void)
 954{
 955        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 956        volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
 957
 958        if (fec_reset(fecp) < 0)
 959                printf ("FEC_RESET_DELAY timeout\n");
 960
 961        /* We use strictly polling mode only
 962         */
 963        fecp->fec_imask = 0;
 964
 965        /* Clear any pending interrupt
 966         */
 967        fecp->fec_ievent = 0xffc0;
 968
 969        /* Now enable the transmit and receive processing
 970         */
 971        fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
 972}
 973
 974void mii_init (void)
 975{
 976        int i;
 977
 978        __mii_init();
 979
 980        /* Setup the pin configuration of the FEC(s)
 981        */
 982        for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
 983                fec_pin_init(ether_fcc_info[i].ether_index);
 984}
 985
 986/*****************************************************************************
 987 * Read and write a MII PHY register, routines used by MII Utilities
 988 *
 989 * FIXME: These routines are expected to return 0 on success, but mii_send
 990 *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 991 *        no PHY connected...
 992 *        For now always return 0.
 993 * FIXME: These routines only work after calling eth_init() at least once!
 994 *        Otherwise they hang in mii_send() !!! Sorry!
 995 *****************************************************************************/
 996
 997int fec8xx_miiphy_read(const char *devname, unsigned char addr,
 998                unsigned char  reg, unsigned short *value)
 999{
1000        short rdreg;    /* register working value */

1001
1002#ifdef MII_DEBUG
1003        printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
1004#endif
1005        rdreg = mii_send(mk_mii_read(addr, reg));
1006
1007        *value = rdreg;
1008#ifdef MII_DEBUG
1009        printf ("0x%04x\n", *value);
1010#endif
1011        return 0;
1012}
1013
1014int fec8xx_miiphy_write(const char *devname, unsigned char  addr,
1015                unsigned char  reg, unsigned short value)
1016{
1017#ifdef MII_DEBUG
1018        printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
1019#endif
1020        (void)mii_send(mk_mii_write(addr, reg, value));
1021
1022#ifdef MII_DEBUG
1023        printf ("0x%04x\n", value);
1024#endif
1025        return 0;
1026}
1027#endif
1028
1029#endif
1030