uboot/arch/powerpc/cpu/mpc8xx/kgdb.S
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   1/*
   2 *  Copyright (C) 2000  Murray Jensen <Murray.Jensen@cmst.csiro.au>
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#include <config.h>
  24#include <command.h>
  25#include <mpc8xx.h>
  26#include <version.h>
  27
  28#define CONFIG_8xx 1            /* needed for Linux kernel header files */
  29#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  30
  31#include <ppc_asm.tmpl>
  32#include <ppc_defs.h>
  33
  34#include <asm/cache.h>
  35#include <asm/mmu.h>
  36
  37#if defined(CONFIG_CMD_KGDB)
  38
  39 /*
  40 * cache flushing routines for kgdb
  41 */
  42
  43        .globl  kgdb_flush_cache_all
  44kgdb_flush_cache_all:
  45        lis     r3, IDC_INVALL@h
  46        mtspr   DC_CST, r3
  47        sync
  48        lis     r3, IDC_INVALL@h
  49        mtspr   IC_CST, r3
  50        SYNC
  51        blr
  52
  53        .globl  kgdb_flush_cache_range
  54kgdb_flush_cache_range:
  55        li      r5,CONFIG_SYS_CACHELINE_SIZE-1
  56        andc    r3,r3,r5
  57        subf    r4,r3,r4
  58        add     r4,r4,r5
  59        srwi.   r4,r4,CONFIG_SYS_CACHELINE_SHIFT
  60        beqlr
  61        mtctr   r4
  62        mr      r6,r3
  631:      dcbst   0,r3
  64        addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
  65        bdnz    1b
  66        sync                            /* wait for dcbst's to get to ram */
  67        mtctr   r4
  682:      icbi    0,r6
  69        addi    r6,r6,CONFIG_SYS_CACHELINE_SIZE
  70        bdnz    2b
  71        SYNC
  72        blr
  73
  74#endif
  75