1/* 2 * MPC85xx Internal Memory Map 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25#ifndef __FSL_FMAN_H__ 26#define __FSL_FMAN_H__ 27 28#include <asm/types.h> 29 30typedef struct fm_bmi_common { 31 u32 fmbm_init; /* BMI initialization */ 32 u32 fmbm_cfg1; /* BMI configuration1 */ 33 u32 fmbm_cfg2; /* BMI configuration2 */ 34 u32 res0[0x5]; 35 u32 fmbm_ievr; /* interrupt event register */ 36 u32 fmbm_ier; /* interrupt enable register */ 37 u32 fmbm_ifr; /* interrupt force register */ 38 u32 res1[0x5]; 39 u32 fmbm_arb[0x8]; /* BMI arbitration */ 40 u32 res2[0x28]; 41 u32 fmbm_gde; /* global debug enable */ 42 u32 fmbm_pp[0x3f]; /* BMI port parameters */ 43 u32 res3; 44 u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */ 45 u32 res4; 46 u32 fmbm_ppid[0x3f];/* port partition ID */ 47} fm_bmi_common_t; 48 49typedef struct fm_qmi_common { 50 u32 fmqm_gc; /* general configuration register */ 51 u32 res0; 52 u32 fmqm_eie; /* error interrupt event register */ 53 u32 fmqm_eien; /* error interrupt enable register */ 54 u32 fmqm_eif; /* error interrupt force register */ 55 u32 fmqm_ie; /* interrupt event register */ 56 u32 fmqm_ien; /* interrupt enable register */ 57 u32 fmqm_if; /* interrupt force register */ 58 u32 fmqm_gs; /* global status register */ 59 u32 fmqm_ts; /* task status register */ 60 u32 fmqm_etfc; /* enqueue total frame counter */ 61 u32 fmqm_dtfc; /* dequeue total frame counter */ 62 u32 fmqm_dc0; /* dequeue counter 0 */ 63 u32 fmqm_dc1; /* dequeue counter 1 */ 64 u32 fmqm_dc2; /* dequeue counter 2 */ 65 u32 fmqm_dc3; /* dequeue counter 3 */ 66 u32 fmqm_dfnoc; /* dequeue FQID not override counter */ 67 u32 fmqm_dfcc; /* dequeue FQID from context counter */ 68 u32 fmqm_dffc; /* dequeue FQID from FD counter */ 69 u32 fmqm_dcc; /* dequeue confirm counter */ 70 u32 res1[0xc]; 71 u32 fmqm_dtrc; /* debug trap configuration register */ 72 u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */ 73 u32 res3[0x2]; 74 u32 res4[0xdc]; /* missing debug regs */ 75} fm_qmi_common_t; 76 77typedef struct fm_bmi { 78 u8 res[1024]; 79} fm_bmi_t; 80 81typedef struct fm_qmi { 82 u8 res[1024]; 83} fm_qmi_t; 84 85struct fm_bmi_rx_port { 86 u32 fmbm_rcfg; /* Rx configuration */ 87 u32 fmbm_rst; /* Rx status */ 88 u32 fmbm_rda; /* Rx DMA attributes */ 89 u32 fmbm_rfp; /* Rx FIFO parameters */ 90 u32 fmbm_rfed; /* Rx frame end data */ 91 u32 fmbm_ricp; /* Rx internal context parameters */ 92 u32 fmbm_rim; /* Rx internal margins */ 93 u32 fmbm_rebm; /* Rx external buffer margins */ 94 u32 fmbm_rfne; /* Rx frame next engine */ 95 u32 fmbm_rfca; /* Rx frame command attributes */ 96 u32 fmbm_rfpne; /* Rx frame parser next engine */ 97 u32 fmbm_rpso; /* Rx parse start offset */ 98 u32 fmbm_rpp; /* Rx policer profile */ 99 u32 fmbm_rccb; /* Rx coarse classification base */ 100 u32 res1[0x2]; 101 u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */ 102 u32 fmbm_rfqid; /* Rx frame queue ID */ 103 u32 fmbm_refqid; /* Rx error frame queue ID */ 104 u32 fmbm_rfsdm; /* Rx frame status discard mask */ 105 u32 fmbm_rfsem; /* Rx frame status error mask */ 106 u32 fmbm_rfene; /* Rx frame enqueue next engine */ 107 u32 res2[0x23]; 108 u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */ 109 u32 fmbm_acnt[0x8]; /* allocate counter */ 110 u32 res3[0x8]; 111 u32 fmbm_cgm[0x8]; /* congestion group map */ 112 u32 fmbm_mpd; /* BMan pool depletion */ 113 u32 res4[0x1F]; 114 u32 fmbm_rstc; /* Rx statistics counters */ 115 u32 fmbm_rfrc; /* Rx frame counters */ 116 u32 fmbm_rfbc; /* Rx bad frames counter */ 117 u32 fmbm_rlfc; /* Rx large frames counter */ 118 u32 fmbm_rffc; /* Rx filter frames counter */ 119 u32 fmbm_rfdc; /* Rx frame discard counter */ 120 u32 fmbm_rfldec; /* Rx frames list DMA error counter */ 121 u32 fmbm_rodc; /* Rx out of buffers discard counter */ 122 u32 fmbm_rbdc; /* Rx buffers deallocate counter */ 123 u32 res5[0x17]; 124 u32 fmbm_rpc; /* Rx performance counters */ 125 u32 fmbm_rpcp; /* Rx performance count parameters */ 126 u32 fmbm_rccn; /* Rx cycle counter */ 127 u32 fmbm_rtuc; /* Rx tasks utilization counter */ 128 u32 fmbm_rrquc; /* Rx receive queue utilization counter */ 129 u32 fmbm_rduc; /* Rx DMA utilization counter */ 130 u32 fmbm_rfuc; /* Rx FIFO utilization counter */ 131 u32 fmbm_rpac; /* Rx pause activation counter */ 132 u32 res6[0x18]; 133 u32 fmbm_rdbg; /* Rx debug configuration */ 134}; 135 136/* FMBM_RCFG - Rx configuration */ 137#define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */ 138#define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */ 139#define FMBM_RCFG_IM 0x01000000 /* independent mode */ 140 141/* FMBM_RST - Rx status */ 142#define FMBM_RST_BSY 0x80000000 /* Rx port is busy */ 143 144/* FMBM_RFCA - Rx frame command attributes */ 145#define FMBM_RFCA_ORDER 0x80000000 146#define FMBM_RFCA_MR_MASK 0x003f0000 147#define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK) 148 149/* FMBM_RSTC - Rx statistics */ 150#define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */ 151 152struct fm_bmi_tx_port { 153 u32 fmbm_tcfg; /* Tx configuration */ 154 u32 fmbm_tst; /* Tx status */ 155 u32 fmbm_tda; /* Tx DMA attributes */ 156 u32 fmbm_tfp; /* Tx FIFO parameters */ 157 u32 fmbm_tfed; /* Tx frame end data */ 158 u32 fmbm_ticp; /* Tx internal context parameters */ 159 u32 fmbm_tfne; /* Tx frame next engine */ 160 u32 fmbm_tfca; /* Tx frame command attributes */ 161 u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */ 162 u32 fmbm_tfeqid;/* Tx error frame queue ID */ 163 u32 fmbm_tfene; /* Tx frame enqueue next engine */ 164 u32 fmbm_trlmts;/* Tx rate limiter scale */ 165 u32 fmbm_trlmt; /* Tx rate limiter */ 166 u32 res0[0x73]; 167 u32 fmbm_tstc; /* Tx statistics counters */ 168 u32 fmbm_tfrc; /* Tx frame counter */ 169 u32 fmbm_tfdc; /* Tx frames discard counter */ 170 u32 fmbm_tfledc;/* Tx frame length error discard counter */ 171 u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */ 172 u32 fmbm_tbdc; /* Tx buffers deallocate counter */ 173 u32 res1[0x1a]; 174 u32 fmbm_tpc; /* Tx performance counters */ 175 u32 fmbm_tpcp; /* Tx performance count parameters */ 176 u32 fmbm_tccn; /* Tx cycle counter */ 177 u32 fmbm_ttuc; /* Tx tasks utilization counter */ 178 u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */ 179 u32 fmbm_tduc; /* Tx DMA utilization counter */ 180 u32 fmbm_tfuc; /* Tx FIFO utilization counter */ 181 u32 res2[0x19]; 182 u32 fmbm_tdcfg; /* Tx debug configuration */ 183}; 184 185/* FMBM_TCFG - Tx configuration */ 186#define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */ 187#define FMBM_TCFG_IM 0x01000000 /* independent mode enable */ 188 189/* FMBM_TST - Tx status */ 190#define FMBM_TST_BSY 0x80000000 /* Tx port is busy */ 191 192/* FMBM_TFCA - Tx frame command attributes */ 193#define FMBM_TFCA_ORDER 0x80000000 194#define FMBM_TFCA_MR_MASK 0x003f0000 195#define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK) 196 197/* FMBM_TSTC - Tx statistics counters */ 198#define FMBM_TSTC_EN 0x80000000 199 200/* FMBM_INIT - BMI initialization register */ 201#define FMBM_INIT_START 0x80000000 /* init internal buffers */ 202 203/* FMBM_CFG1 - BMI configuration 1 */ 204#define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */ 205#define FMBM_CFG1_FBPS_SHIFT 16 206#define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */ 207 208/* FMBM_IEVR - interrupt event */ 209#define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */ 210#define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */ 211#define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */ 212#define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC) 213 214/* FMBM_IER - interrupt enable */ 215#define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */ 216#define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */ 217#define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */ 218 219#define FMBM_IER_DISABLE_ALL 0x00000000 220 221/* FMBM_PP - BMI Port Parameters */ 222#define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */ 223#define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK) 224#define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */ 225#define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK) 226 227/* FMBM_PFS - BMI Port FIFO Size */ 228#define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */ 229#define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK) 230 231/* FMQM_GC - global configuration */ 232#define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */ 233#define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */ 234#define FMQM_GC_STEN 0x10000000 /* enable global stat counters */ 235#define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */ 236#define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS) 237#define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */ 238#define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK) 239 240/* FMQM_EIE - error interrupt event register */ 241#define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */ 242#define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */ 243#define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE) 244 245/* FMQM_EIEN - error interrupt enable register */ 246#define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */ 247#define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */ 248#define FMQM_EIEN_DISABLE_ALL 0x00000000 249 250/* FMQM_IE - interrupt event register */ 251#define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */ 252#define FMQM_IE_CLEAR_ALL FMQM_IE_SEE 253 254/* FMQM_IEN - interrupt enable register */ 255#define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */ 256#define FMQM_IEN_DISABLE_ALL 0x00000000 257 258/* NIA - next invoked action */ 259#define NIA_ENG_RISC 0x00000000 260#define NIA_ENG_MASK 0x007c0000 261 262/* action code */ 263#define NIA_RISC_AC_CC 0x00000006 264#define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */ 265#define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */ 266#define NIA_RISC_AC_HC 0x0000000c 267 268typedef struct fm_parser { 269 u8 res[1024]; 270} fm_parser_t; 271 272typedef struct fm_policer { 273 u8 res[4*1024]; 274} fm_policer_t; 275 276typedef struct fm_keygen { 277 u8 res[4*1024]; 278} fm_keygen_t; 279 280typedef struct fm_dma { 281 u32 fmdmsr; /* status register */ 282 u32 fmdmmr; /* mode register */ 283 u32 fmdmtr; /* bus threshold register */ 284 u32 fmdmhy; /* bus hysteresis register */ 285 u32 fmdmsetr; /* SOS emergency threshold register */ 286 u32 fmdmtah; /* transfer bus address high register */ 287 u32 fmdmtal; /* transfer bus address low register */ 288 u32 fmdmtcid; /* transfer bus communication ID register */ 289 u32 fmdmra; /* DMA bus internal ram address register */ 290 u32 fmdmrd; /* DMA bus internal ram data register */ 291 u32 res0[0xb]; 292 u32 fmdmdcr; /* debug counter */ 293 u32 fmdmemsr; /* emrgency smoother register */ 294 u32 res1; 295 u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */ 296 u32 res[0x3c8]; 297} fm_dma_t; 298 299/* FMDMSR - Fman DMA status register */ 300#define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */ 301#define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */ 302#define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */ 303#define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */ 304#define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */ 305#define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */ 306#define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */ 307#define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */ 308#define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */ 309#define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */ 310 311#define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \ 312 | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \ 313 | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \ 314 | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \ 315 | FMDMSR_SPDAT_FECC) 316 317/* FMDMMR - FMan DMA mode register */ 318#define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */ 319 320typedef struct fm_fpm { 321 u32 fpmtnc; /* TNUM control */ 322 u32 fpmprc; /* Port_ID control */ 323 u32 res0; 324 u32 fpmflc; /* flush control */ 325 u32 fpmdis1; /* dispatch thresholds1 */ 326 u32 fpmdis2; /* dispatch thresholds2 */ 327 u32 fmepi; /* error pending interrupts */ 328 u32 fmrie; /* rams interrupt enable */ 329 u32 fpmfcevent[0x4];/* FMan controller event 0-3 */ 330 u32 res1[0x4]; 331 u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */ 332 u32 res2[0x4]; 333 u32 fpmtsc1; /* timestamp control1 */ 334 u32 fpmtsc2; /* timestamp control2 */ 335 u32 fpmtsp; /* time stamp */ 336 u32 fpmtsf; /* time stamp fraction */ 337 u32 fpmrcr; /* rams control and event */ 338 u32 res3[0x3]; 339 u32 fpmdrd[0x4]; /* data_ram data 0-3 */ 340 u32 res4[0xc]; 341 u32 fpmdra; /* data ram access */ 342 u32 fm_ip_rev_1; /* IP block revision 1 */ 343 u32 fm_ip_rev_2; /* IP block revision 2 */ 344 u32 fmrstc; /* reset command */ 345 u32 fmcld; /* classifier debug control */ 346 u32 fmnpi; /* normal pending interrupts */ 347 u32 res5; 348 u32 fmfpee; /* event and enable */ 349 u32 fpmcev[0x4]; /* CPU event 0-3 */ 350 u32 res6[0x4]; 351 u32 fmfp_ps[0x40]; /* port status */ 352 u32 res7[0x260]; 353 u32 fpmts[0x80]; /* task status */ 354 u32 res8[0xa0]; 355} fm_fpm_t; 356 357/* FMFP_PRC - FPM Port_ID Control Register */ 358#define FMFPPRC_PORTID_MASK 0x3f000000 359#define FMFPPRC_PORTID_SHIFT 24 360#define FMFPPRC_ORA_SHIFT 16 361#define FMFPPRC_RISC1 0x00000001 362#define FMFPPRC_RISC2 0x00000002 363#define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2) 364 365/* FPM Flush Control Register */ 366#define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */ 367 368/* FMFP_EE - FPM event and enable register */ 369#define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */ 370#define FMFPEE_STL 0x40000000 /* stall of task ... */ 371#define FMFPEE_SECC 0x20000000 /* single ECC error */ 372#define FMFPEE_RFM 0x00010000 /* release FMan */ 373#define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */ 374#define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */ 375#define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */ 376#define FMFPEE_EHM 0x00000008 /* external halt enable */ 377#define FMFPEE_UEC 0x00000004 /* FMan is not halted */ 378#define FMFPEE_CER 0x00000002 /* only errornous task stalled */ 379#define FMFPEE_DER 0x00000001 /* DMA error is just reported */ 380 381#define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \ 382 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \ 383 FMFPEE_DER | FMFPEE_RFM) 384 385/* FMFP_RCR - FMan Rams Control and Event */ 386#define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */ 387#define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */ 388 389typedef struct fm_imem { 390 u32 iadd; /* instruction address register */ 391 u32 idata; /* instruction data register */ 392 u32 itcfg; /* timing config register */ 393 u32 iready; /* ready register */ 394 u8 res[0xff0]; 395} fm_imem_t; 396#define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */ 397#define IRAM_READY 0x80000000 /* ready to use */ 398 399typedef struct fm_soft_parser { 400 u8 res[4*1024]; 401} fm_soft_parser_t; 402 403typedef struct fm_dtesc { 404 u8 res[4*1024]; 405} fm_dtsec_t; 406 407typedef struct fm_mdio { 408 u8 res0[0x120]; 409 u32 miimcfg; /* MII management configuration reg */ 410 u32 miimcom; /* MII management command reg */ 411 u32 miimadd; /* MII management address reg */ 412 u32 miimcon; /* MII management control reg */ 413 u32 miimstat; /* MII management status reg */ 414 u32 miimind; /* MII management indication reg */ 415 u8 res1[0x1000 - 0x138]; 416} fm_mdio_t; 417 418typedef struct fm_10gec { 419 u8 res[4*1024]; 420} fm_10gec_t; 421 422typedef struct fm_10gec_mdio { 423 u8 res[4*1024]; 424} fm_10gec_mdio_t; 425 426typedef struct fm_1588 { 427 u8 res[4*1024]; 428} fm_1588_t; 429 430typedef struct ccsr_fman { 431 u8 muram[0x80000]; 432 fm_bmi_common_t fm_bmi_common; 433 fm_qmi_common_t fm_qmi_common; 434 u8 res0[2048]; 435 struct { 436 fm_bmi_t fm_bmi; 437 fm_qmi_t fm_qmi; 438 fm_parser_t fm_parser; 439 u8 res[1024]; 440 } port[63]; 441 fm_policer_t fm_policer; 442 fm_keygen_t fm_keygen; 443 fm_dma_t fm_dma; 444 fm_fpm_t fm_fpm; 445 fm_imem_t fm_imem; 446 u8 res1[8*1024]; 447 fm_soft_parser_t fm_soft_parser; 448 u8 res2[96*1024]; 449 struct { 450 fm_dtsec_t fm_dtesc; 451 fm_mdio_t fm_mdio; 452 } mac_1g[8]; /* support up to 8 1g controllers */ 453 struct { 454 fm_10gec_t fm_10gec; 455 fm_10gec_mdio_t fm_10gec_mdio; 456 } mac_10g[1]; 457 u8 res4[48*1024]; 458 fm_1588_t fm_1588; 459 u8 res5[4*1024]; 460} ccsr_fman_t; 461 462#endif /*__FSL_FMAN_H__*/ 463