uboot/board/cm_t35/cm_t35.c
<<
>>
Prefs 
   1/*
   2 * (C) Copyright 2011
   3 * CompuLab, Ltd. <www.compulab.co.il>
   4 *
   5 * Authors: Mike Rapoport <mike@compulab.co.il>
   6 *          Igor Grinberg <grinberg@compulab.co.il>
   7 *
   8 * Derived from omap3evm and Beagle Board by
   9 *      Manikandan Pillai <mani.pillai@ti.com>
  10 *      Richard Woodruff <r-woodruff2@ti.com>
  11 *      Syed Mohammed Khasim <x0khasim@ti.com>
  12 *
  13 * See file CREDITS for list of people who contributed to this
  14 * project.
  15 *
  16 * This program is free software; you can redistribute it and/or
  17 * modify it under the terms of the GNU General Public License as
  18 * published by the Free Software Foundation; either version 2 of
  19 * the License, or (at your option) any later version.
  20 *
  21 * This program is distributed in the hope that it will be useful,
  22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24 * GNU General Public License for more details.
  25 *
  26 * You should have received a copy of the GNU General Public License
  27 * along with this program; if not, write to the Free Software
  28 * Foundation, Inc.
  29 */
  30
  31#include <common.h>
  32#include <status_led.h>
  33#include <netdev.h>
  34#include <net.h>
  35#include <i2c.h>
  36#include <twl4030.h>
  37
  38#include <asm/io.h>
  39#include <asm/arch/mem.h>
  40#include <asm/arch/mux.h>
  41#include <asm/arch/mmc_host_def.h>
  42#include <asm/arch/sys_proto.h>
  43#include <asm/mach-types.h>
  44
  45DECLARE_GLOBAL_DATA_PTR;
  46
  47const omap3_sysinfo sysinfo = {
  48        DDR_DISCRETE,
  49        "CM-T3x board",
  50        "NAND",
  51};
  52
  53static u32 gpmc_net_config[GPMC_MAX_REG] = {
  54        NET_GPMC_CONFIG1,
  55        NET_GPMC_CONFIG2,
  56        NET_GPMC_CONFIG3,
  57        NET_GPMC_CONFIG4,
  58        NET_GPMC_CONFIG5,
  59        NET_GPMC_CONFIG6,
  60        0
  61};
  62
  63static u32 gpmc_nand_config[GPMC_MAX_REG] = {
  64        SMNAND_GPMC_CONFIG1,
  65        SMNAND_GPMC_CONFIG2,
  66        SMNAND_GPMC_CONFIG3,
  67        SMNAND_GPMC_CONFIG4,
  68        SMNAND_GPMC_CONFIG5,
  69        SMNAND_GPMC_CONFIG6,
  70        0,
  71};
  72
  73/*
  74 * Routine: board_init
  75 * Description: Early hardware init.
  76 */
  77int board_init(void)
  78{
  79        gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  80
  81        enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
  82                              CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
  83
  84        /* board id for Linux */
  85        if (get_cpu_family() == CPU_OMAP34XX)
  86                gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
  87        else
  88                gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
  89
  90        /* boot param addr */
  91        gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  92
  93#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  94        status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  95#endif
  96
  97        return 0;
  98}
  99
 100/*
 101 * Routine: misc_init_r
 102 * Description: display die ID
 103 */
 104int misc_init_r(void)
 105{
 106        dieid_num_r();
 107
 108        return 0;
 109}
 110
 111/*
 112 * Routine: set_muxconf_regs
 113 * Description: Setting up the configuration Mux registers specific to the
 114 *              hardware. Many pins need to be moved from protect to primary
 115 *              mode.
 116 */
 117static void cm_t3x_set_common_muxconf(void)
 118{
 119        /* SDRC */
 120        MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)); /*SDRC_D0*/
 121        MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)); /*SDRC_D1*/
 122        MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)); /*SDRC_D2*/
 123        MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)); /*SDRC_D3*/
 124        MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)); /*SDRC_D4*/
 125        MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)); /*SDRC_D5*/
 126        MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)); /*SDRC_D6*/
 127        MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)); /*SDRC_D7*/
 128        MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)); /*SDRC_D8*/
 129        MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)); /*SDRC_D9*/
 130        MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)); /*SDRC_D10*/
 131        MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)); /*SDRC_D11*/
 132        MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)); /*SDRC_D12*/
 133        MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)); /*SDRC_D13*/
 134        MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)); /*SDRC_D14*/
 135        MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)); /*SDRC_D15*/
 136        MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)); /*SDRC_D16*/
 137        MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)); /*SDRC_D17*/
 138        MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)); /*SDRC_D18*/
 139        MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)); /*SDRC_D19*/
 140        MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)); /*SDRC_D20*/
 141        MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)); /*SDRC_D21*/
 142        MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)); /*SDRC_D22*/
 143        MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)); /*SDRC_D23*/
 144        MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)); /*SDRC_D24*/
 145        MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)); /*SDRC_D25*/
 146        MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)); /*SDRC_D26*/
 147        MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)); /*SDRC_D27*/
 148        MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)); /*SDRC_D28*/
 149        MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)); /*SDRC_D29*/
 150        MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)); /*SDRC_D30*/
 151        MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)); /*SDRC_D31*/
 152        MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
 153        MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
 154        MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
 155        MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
 156        MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
 157        MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
 158        MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
 159
 160        /* GPMC */
 161        MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
 162        MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0)); /*GPMC_A2*/
 163        MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0)); /*GPMC_A3*/
 164        MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0)); /*GPMC_A4*/
 165        MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0)); /*GPMC_A5*/
 166        MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0)); /*GPMC_A6*/
 167        MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0)); /*GPMC_A7*/
 168        MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0)); /*GPMC_A8*/
 169        MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0)); /*GPMC_A9*/
 170        MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0)); /*GPMC_A10*/
 171        MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0)); /*GPMC_D0*/
 172        MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0)); /*GPMC_D1*/
 173        MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0)); /*GPMC_D2*/
 174        MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0)); /*GPMC_D3*/
 175        MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0)); /*GPMC_D4*/
 176        MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0)); /*GPMC_D5*/
 177        MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0)); /*GPMC_D6*/
 178        MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0)); /*GPMC_D7*/
 179        MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0)); /*GPMC_D8*/
 180        MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0)); /*GPMC_D9*/
 181        MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0)); /*GPMC_D10*/
 182        MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0)); /*GPMC_D11*/
 183        MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0)); /*GPMC_D12*/
 184        MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0)); /*GPMC_D13*/
 185        MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0)); /*GPMC_D14*/
 186        MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0)); /*GPMC_D15*/
 187        MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/
 188
 189        /* SB-T35 Ethernet */
 190        MUX_VAL(CP(GPMC_NCS4),          (IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/
 191
 192        /* CM-T3x Ethernet */
 193        MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
 194        MUX_VAL(CP(GPMC_CLK),           (IEN  | PTD | DIS | M4)); /*GPIO_59*/
 195        MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
 196        MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)); /*nOE*/
 197        MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)); /*nWE*/
 198        MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0)); /*nBE0_CLE*/
 199        MUX_VAL(CP(GPMC_NBE1),          (IDIS | PTD | DIS | M4)); /*GPIO_61*/
 200        MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)); /*nWP*/
 201        MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)); /*WAIT0*/
 202
 203        /* DSS */
 204        MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
 205        MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
 206        MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
 207        MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
 208        MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
 209        MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
 210        MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
 211        MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
 212        MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
 213        MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
 214        MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
 215        MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
 216        MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
 217        MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
 218        MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
 219        MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
 220
 221        /* serial interface */
 222        MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)); /*UART3_RX*/
 223        MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)); /*UART3_TX*/
 224
 225        /* mUSB */
 226        MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)); /*HSUSB0_CLK*/
 227        MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)); /*HSUSB0_STP*/
 228        MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)); /*HSUSB0_DIR*/
 229        MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)); /*HSUSB0_NXT*/
 230        MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA0*/
 231        MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA1*/
 232        MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA2*/
 233        MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA3*/
 234        MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA4*/
 235        MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA5*/
 236        MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA6*/
 237        MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA7*/
 238
 239        /* I2C1 */
 240        MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
 241        MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)); /*I2C1_SDA*/
 242
 243        /* control and debug */
 244        MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)); /*SYS_32K*/
 245        MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)); /*SYS_CLKREQ*/
 246        MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)); /*SYS_nIRQ*/
 247        MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)); /*OFF_MODE*/
 248        MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)); /*CLKOUT1*/
 249        MUX_VAL(CP(SYS_CLKOUT2),        (IDIS | PTU | DIS | M4)); /*green LED*/
 250        MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
 251        MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
 252        MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
 253        MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
 254
 255        /* MMC1 */
 256        MUX_VAL(CP(MMC1_CLK),           (IDIS | PTU | EN  | M0)); /*MMC1_CLK*/
 257        MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | EN  | M0)); /*MMC1_CMD*/
 258        MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT0*/
 259        MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
 260        MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
 261        MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
 262}
 263
 264static void cm_t35_set_muxconf(void)
 265{
 266        /* DSS */
 267        MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
 268        MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
 269        MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
 270        MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
 271        MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
 272        MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
 273
 274        MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
 275        MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
 276        MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
 277        MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
 278        MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
 279        MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
 280
 281        /* MMC1 */
 282        MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT4*/
 283        MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT5*/
 284        MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT6*/
 285        MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M0)); /*MMC1_DAT7*/
 286}
 287
 288static void cm_t3730_set_muxconf(void)
 289{
 290        /* DSS */
 291        MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
 292        MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
 293        MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
 294        MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
 295        MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
 296        MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
 297
 298        MUX_VAL(CP(SYS_BOOT0),          (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
 299        MUX_VAL(CP(SYS_BOOT1),          (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
 300        MUX_VAL(CP(SYS_BOOT3),          (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
 301        MUX_VAL(CP(SYS_BOOT4),          (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
 302        MUX_VAL(CP(SYS_BOOT5),          (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
 303        MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
 304}
 305
 306void set_muxconf_regs(void)
 307{
 308        cm_t3x_set_common_muxconf();
 309
 310        if (get_cpu_family() == CPU_OMAP34XX)
 311                cm_t35_set_muxconf();
 312        else
 313                cm_t3730_set_muxconf();
 314}
 315
 316#ifdef CONFIG_GENERIC_MMC
 317int board_mmc_init(bd_t *bis)
 318{
 319        omap_mmc_init(0);
 320        return 0;
 321}
 322#endif
 323
 324/*
 325 * Routine: setup_net_chip_gmpc
 326 * Description: Setting up the configuration GPMC registers specific to the
 327 *              Ethernet hardware.
 328 */
 329static void setup_net_chip_gmpc(void)
 330{
 331        struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 332
 333        enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
 334                              CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
 335        enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
 336                              SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
 337
 338        /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 339        writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 340
 341        /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 342        writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 343
 344        /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 345        writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 346                &ctrl_base->gpmc_nadv_ale);
 347}
 348
 349#ifdef CONFIG_DRIVER_OMAP34XX_I2C
 350/*
 351 * Routine: reset_net_chip
 352 * Description: reset the Ethernet controller via TPS65930 GPIO
 353 */
 354static void reset_net_chip(void)
 355{
 356        /* Set GPIO1 of TPS65930 as output */
 357        twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 358                             TWL4030_BASEADD_GPIO+0x03);
 359        /* Send a pulse on the GPIO pin */
 360        twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 361                             TWL4030_BASEADD_GPIO+0x0C);
 362        udelay(1);
 363        twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 364                             TWL4030_BASEADD_GPIO+0x09);
 365        udelay(1);
 366        twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 367                             TWL4030_BASEADD_GPIO+0x0C);
 368}
 369#else
 370static inline void reset_net_chip(void) {}
 371#endif
 372
 373/*
 374 * Routine: handle_mac_address
 375 * Description: prepare MAC address for on-board Ethernet.
 376 */
 377static int handle_mac_address(void)
 378{
 379        unsigned char enetaddr[6];
 380        int rc;
 381
 382        rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 383        if (rc)
 384                return 0;
 385
 386#ifdef CONFIG_DRIVER_OMAP34XX_I2C
 387        rc = i2c_read(0x50, 0, 1, enetaddr, 6);
 388        if (rc)
 389                return rc;
 390#endif
 391
 392        if (!is_valid_ether_addr(enetaddr))
 393                return -1;
 394
 395        return eth_setenv_enetaddr("ethaddr", enetaddr);
 396}
 397
 398
 399/*
 400 * Routine: board_eth_init
 401 * Description: initialize module and base-board Ethernet chips
 402 */
 403int board_eth_init(bd_t *bis)
 404{
 405        int rc = 0, rc1 = 0;
 406
 407#ifdef CONFIG_SMC911X
 408        setup_net_chip_gmpc();
 409        reset_net_chip();
 410
 411        rc1 = handle_mac_address();
 412        if (rc1)
 413                printf("CM-T3x: No MAC address found\n");
 414
 415        rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
 416        if (rc1 > 0)
 417                rc++;
 418
 419        rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
 420        if (rc1 > 0)
 421                rc++;
 422#endif
 423
 424        return rc;
 425}
 426
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.