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23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/immap_86xx.h>
28#include <asm/fsl_pci.h>
29#include <asm/fsl_ddr_sdram.h>
30#include <asm/fsl_serdes.h>
31#include <i2c.h>
32#include <asm/io.h>
33#include <libfdt.h>
34#include <fdt_support.h>
35#include <spd_sdram.h>
36#include <netdev.h>
37
38void sdram_init(void);
39phys_size_t fixed_sdram(void);
40int mpc8610hpcd_diu_init(void);
41
42
43
44int board_early_init_f(void)
45{
46 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
47 volatile ccsr_gur_t *gur = &immap->im_gur;
48
49 gur->gpiocr |= 0x88aa5500;
50
51 return 0;
52}
53
54int misc_init_r(void)
55{
56 u8 tmp_val, version;
57 u8 *pixis_base = (u8 *)PIXIS_BASE;
58
59
60 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
61 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
62
63
64 version = in_8(pixis_base + PIXIS_PVER);
65 if(version >= 0x07) {
66 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
67 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
68 }
69
70
71
72
73
74 tmp_val = 0xBF;
75 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
76
77 tmp_val = 0;
78 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
79 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
80
81 tmp_val = 0x10;
82 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
83
84 tmp_val = 0;
85 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
86 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
87
88 return 0;
89}
90
91int checkboard(void)
92{
93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
94 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
95 u8 *pixis_base = (u8 *)PIXIS_BASE;
96
97 printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
98 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
99 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
100 in_8(pixis_base + PIXIS_PVER));
101
102
103
104
105
106
107
108 switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
109 case 0:
110 puts("vBank: Standard\n");
111 break;
112 case 0x40:
113 puts("Promjet\n");
114 break;
115 case 0x80:
116 puts("NAND\n");
117 break;
118 case 0xC0:
119 puts("vBank: Alternate\n");
120 break;
121 }
122
123 mcm->abcr |= 0x00010000;
124 mcm->hpmr3 = 0x80000008;
125 mcm->hpmr0 = 0;
126 mcm->hpmr1 = 0;
127 mcm->hpmr2 = 0;
128 mcm->hpmr4 = 0;
129 mcm->hpmr5 = 0;
130
131 return 0;
132}
133
134
135phys_size_t
136initdram(int board_type)
137{
138 phys_size_t dram_size = 0;
139
140#if defined(CONFIG_SPD_EEPROM)
141 dram_size = fsl_ddr_sdram();
142#else
143 dram_size = fixed_sdram();
144#endif
145
146 setup_ddr_bat(dram_size);
147
148 debug(" DDR: ");
149 return dram_size;
150}
151
152
153#if !defined(CONFIG_SPD_EEPROM)
154
155
156
157
158phys_size_t fixed_sdram(void)
159{
160#if !defined(CONFIG_SYS_RAMBOOT)
161 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
162 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
163 uint d_init;
164
165 ddr->cs0_bnds = 0x0000001f;
166 ddr->cs0_config = 0x80010202;
167
168 ddr->timing_cfg_3 = 0x00000000;
169 ddr->timing_cfg_0 = 0x00260802;
170 ddr->timing_cfg_1 = 0x3935d322;
171 ddr->timing_cfg_2 = 0x14904cc8;
172 ddr->sdram_mode = 0x00480432;
173 ddr->sdram_mode_2 = 0x00000000;
174 ddr->sdram_interval = 0x06180fff;
175 ddr->sdram_data_init = 0xDEADBEEF;
176 ddr->sdram_clk_cntl = 0x03800000;
177 ddr->sdram_cfg_2 = 0x04400010;
178
179#if defined(CONFIG_DDR_ECC)
180 ddr->err_int_en = 0x0000000d;
181 ddr->err_disable = 0x00000000;
182 ddr->err_sbe = 0x00010000;
183#endif
184 asm("sync;isync");
185
186 udelay(500);
187
188 ddr->sdram_cfg = 0xc3000000;
189
190
191#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
192 d_init = 1;
193 debug("DDR - 1st controller: memory initializing\n");
194
195
196
197
198 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
199 udelay(1000);
200
201 debug("DDR: memory initialized\n\n");
202 asm("sync; isync");
203 udelay(500);
204#endif
205
206 return 512 * 1024 * 1024;
207#endif
208 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
209}
210
211#endif
212
213#if defined(CONFIG_PCI)
214
215
216
217
218#ifndef CONFIG_PCI_PNP
219static struct pci_config_table pci_fsl86xxads_config_table[] = {
220 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
221 PCI_IDSEL_NUMBER, PCI_ANY_ID,
222 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
223 PCI_ENET0_MEMADDR,
224 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
225 {}
226};
227#endif
228
229
230static struct pci_controller pci1_hose;
231#endif
232
233void pci_init_board(void)
234{
235 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
236 volatile ccsr_gur_t *gur = &immap->im_gur;
237 struct fsl_pci_info pci_info;
238 u32 devdisr;
239 int first_free_busno;
240 int pci_agent;
241
242 devdisr = in_be32(&gur->devdisr);
243
244 first_free_busno = fsl_pcie_init_board(0);
245
246#ifdef CONFIG_PCI1
247 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
248 SET_STD_PCI_INFO(pci_info, 1);
249 set_next_law(pci_info.mem_phys,
250 law_size_bits(pci_info.mem_size), pci_info.law);
251 set_next_law(pci_info.io_phys,
252 law_size_bits(pci_info.io_size), pci_info.law);
253
254 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
255 printf("PCI: connected to PCI slots as %s" \
256 " (base address %lx)\n",
257 pci_agent ? "Agent" : "Host",
258 pci_info.regs);
259#ifndef CONFIG_PCI_PNP
260 pci1_hose.config_table = pci_mpc86xxcts_config_table;
261#endif
262 first_free_busno = fsl_pci_init_port(&pci_info,
263 &pci1_hose, first_free_busno);
264 } else {
265 printf("PCI: disabled\n");
266 }
267
268 puts("\n");
269#else
270 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1);
271#endif
272
273 fsl_pcie_init_board(first_free_busno);
274}
275
276#if defined(CONFIG_OF_BOARD_SETUP)
277void
278ft_board_setup(void *blob, bd_t *bd)
279{
280 ft_cpu_setup(blob, bd);
281
282 FT_FSL_PCI_SETUP;
283}
284#endif
285
286
287
288
289
290
291unsigned long
292get_board_sys_clk(ulong dummy)
293{
294 u8 i;
295 ulong val = 0;
296 u8 *pixis_base = (u8 *)PIXIS_BASE;
297
298 i = in_8(pixis_base + PIXIS_SPD);
299 i &= 0x07;
300
301 switch (i) {
302 case 0:
303 val = 33333000;
304 break;
305 case 1:
306 val = 39999600;
307 break;
308 case 2:
309 val = 49999500;
310 break;
311 case 3:
312 val = 66666000;
313 break;
314 case 4:
315 val = 83332500;
316 break;
317 case 5:
318 val = 99999000;
319 break;
320 case 6:
321 val = 133332000;
322 break;
323 case 7:
324 val = 166665000;
325 break;
326 }
327
328 return val;
329}
330
331int board_eth_init(bd_t *bis)
332{
333 return pci_eth_init(bis);
334}
335
336void board_reset(void)
337{
338 u8 *pixis_base = (u8 *)PIXIS_BASE;
339
340 out_8(pixis_base + PIXIS_RST, 0);
341
342 while (1)
343 ;
344}
345