LXR uboot/drivers/mtd/nand/omap

   1/*
   2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3 * Rohit Choraria <rohitkc@ti.com>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/io.h>
  26#include <asm/errno.h>
  27#include <asm/arch/mem.h>
  28#include <asm/arch/omap_gpmc.h>
  29#include <linux/mtd/nand_ecc.h>
  30#include <nand.h>
  31
  32static uint8_t cs;
  33static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
  34
  35/*
  36 * omap_nand_hwcontrol - Set the address pointers corretly for the
  37 *                      following address/data/command operation
  38 */
  39static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  40                                uint32_t ctrl)
  41{
  42        register struct nand_chip *this = mtd->priv;
  43
  44        /*
  45         * Point the IO_ADDR to DATA and ADDRESS registers instead
  46         * of chip address
  47         */
  48        switch (ctrl) {
  49        case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  50                this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  51                break;
  52        case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  53                this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  54                break;
  55        case NAND_CTRL_CHANGE | NAND_NCE:
  56                this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  57                break;
  58        }
  59
  60        if (cmd != NAND_CMD_NONE)
  61                writeb(cmd, this->IO_ADDR_W);
  62}
  63
  64#ifdef CONFIG_SPL_BUILD
  65/* Check wait pin as dev ready indicator */
  66int omap_spl_dev_ready(struct mtd_info *mtd)
  67{
  68        return gpmc_cfg->status & (1 << 8);
  69}
  70#endif
  71
  72/*
  73 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
  74 *                   GPMC controller
  75 * @mtd:        MTD device structure
  76 *
  77 */
  78static void omap_hwecc_init(struct nand_chip *chip)
  79{
  80        /*
  81         * Init ECC Control Register
  82         * Clear all ECC | Enable Reg1
  83         */
  84        writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
  85        writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
  86}
  87
  88/*
  89 * gen_true_ecc - This function will generate true ECC value, which
  90 * can be used when correcting data read from NAND flash memory core
  91 *
  92 * @ecc_buf:    buffer to store ecc code
  93 *
  94 * @return:     re-formatted ECC value
  95 */
  96static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  97{
  98        return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  99                ((ecc_buf[2] & 0x0F) << 8);
 100}
 101
 102/*
 103 * omap_correct_data - Compares the ecc read from nand spare area with ECC
 104 * registers values and corrects one bit error if it has occured
 105 * Further details can be had from OMAP TRM and the following selected links:
 106 * http://en.wikipedia.org/wiki/Hamming_code
 107 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 108 *
 109 * @mtd:                 MTD device structure
 110 * @dat:                 page data
 111 * @read_ecc:            ecc read from nand flash
 112 * @calc_ecc:            ecc read from ECC registers
 113 *
 114 * @return 0 if data is OK or corrected, else returns -1
 115 */
 116static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 117                                uint8_t *read_ecc, uint8_t *calc_ecc)
 118{
 119        uint32_t orig_ecc, new_ecc, res, hm;
 120        uint16_t parity_bits, byte;
 121        uint8_t bit;
 122
 123        /* Regenerate the orginal ECC */
 124        orig_ecc = gen_true_ecc(read_ecc);
 125        new_ecc = gen_true_ecc(calc_ecc);
 126        /* Get the XOR of real ecc */
 127        res = orig_ecc ^ new_ecc;
 128        if (res) {
 129                /* Get the hamming width */
 130                hm = hweight32(res);
 131                /* Single bit errors can be corrected! */
 132                if (hm == 12) {
 133                        /* Correctable data! */
 134                        parity_bits = res >> 16;
 135                        bit = (parity_bits & 0x7);
 136                        byte = (parity_bits >> 3) & 0x1FF;
 137                        /* Flip the bit to correct */
 138                        dat[byte] ^= (0x1 << bit);
 139                } else if (hm == 1) {
 140                        printf("Error: Ecc is wrong\n");
 141                        /* ECC itself is corrupted */
 142                        return 2;
 143                } else {
 144                        /*
 145                         * hm distance != parity pairs OR one, could mean 2 bit
 146                         * error OR potentially be on a blank page..
 147                         * orig_ecc: contains spare area data from nand flash.
 148                         * new_ecc: generated ecc while reading data area.
 149                         * Note: if the ecc = 0, all data bits from which it was
 150                         * generated are 0xFF.
 151                         * The 3 byte(24 bits) ecc is generated per 512byte
 152                         * chunk of a page. If orig_ecc(from spare area)
 153                         * is 0xFF && new_ecc(computed now from data area)=0x0,
 154                         * this means that data area is 0xFF and spare area is
 155                         * 0xFF. A sure sign of a erased page!
 156                         */
 157                        if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 158                                return 0;
 159                        printf("Error: Bad compare! failed\n");
 160                        /* detected 2 bit error */
 161                        return -1;
 162                }
 163        }
 164        return 0;
 165}
 166
 167/*
 168 *  omap_calculate_ecc - Generate non-inverted ECC bytes.
 169 *
 170 *  Using noninverted ECC can be considered ugly since writing a blank
 171 *  page ie. padding will clear the ECC bytes. This is no problem as
 172 *  long nobody is trying to write data on the seemingly unused page.
 173 *  Reading an erased page will produce an ECC mismatch between
 174 *  generated and read ECC bytes that has to be dealt with separately.
 175 *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 176 *  is used, the result of read will be 0x0 while the ECC offsets of the
 177 *  spare area will be 0xFF which will result in an ECC mismatch.
 178 *  @mtd:       MTD structure
 179 *  @dat:       unused
 180 *  @ecc_code:  ecc_code buffer
 181 */
 182static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 183                                uint8_t *ecc_code)
 184{
 185        u_int32_t val;
 186
 187        /* Start Reading from HW ECC1_Result = 0x200 */
 188        val = readl(&gpmc_cfg->ecc1_result);
 189
 190        ecc_code[0] = val & 0xFF;
 191        ecc_code[1] = (val >> 16) & 0xFF;
 192        ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 193
 194        /*
 195         * Stop reading anymore ECC vals and clear old results
 196         * enable will be called if more reads are required
 197         */
 198        writel(0x000, &gpmc_cfg->ecc_config);
 199
 200        return 0;
 201}
 202
 203/*
 204 * omap_enable_ecc - This function enables the hardware ecc functionality
 205 * @mtd:        MTD device structure
 206 * @mode:       Read/Write mode
 207 */
 208static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 209{
 210        struct nand_chip *chip = mtd->priv;
 211        uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
 212
 213        switch (mode) {
 214        case NAND_ECC_READ:
 215        case NAND_ECC_WRITE:
 216                /* Clear the ecc result registers, select ecc reg as 1 */
 217                writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 218
 219                /*
 220                 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
 221                 * tell all regs to generate size0 sized regs
 222                 * we just have a single ECC engine for all CS
 223                 */
 224                writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
 225                        &gpmc_cfg->ecc_size_config);
 226                val = (dev_width << 7) | (cs << 1) | (0x1);
 227                writel(val, &gpmc_cfg->ecc_config);
 228                break;
 229        default:
 230                printf("Error: Unrecognized Mode[%d]!\n", mode);
 231                break;
 232        }
 233}
 234
 235#ifndef CONFIG_SPL_BUILD
 236/*
 237 * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
 238 * The default is to come up on s/w ecc
 239 *
 240 * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
 241 *
 242 */
 243void omap_nand_switch_ecc(int32_t hardware)
 244{
 245        struct nand_chip *nand;
 246        struct mtd_info *mtd;
 247
 248        if (nand_curr_device < 0 ||
 249            nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 250            !nand_info[nand_curr_device].name) {
 251                printf("Error: Can't switch ecc, no devices available\n");
 252                return;
 253        }
 254
 255        mtd = &nand_info[nand_curr_device];
 256        nand = mtd->priv;
 257
 258        nand->options |= NAND_OWN_BUFFERS;
 259
 260        /* Reset ecc interface */
 261        nand->ecc.read_page = NULL;
 262        nand->ecc.write_page = NULL;
 263        nand->ecc.read_oob = NULL;
 264        nand->ecc.write_oob = NULL;
 265        nand->ecc.hwctl = NULL;
 266        nand->ecc.correct = NULL;
 267        nand->ecc.calculate = NULL;
 268
 269        /* Setup the ecc configurations again */
 270        if (hardware) {
 271                nand->ecc.mode = NAND_ECC_HW;
 272                nand->ecc.layout = &hw_nand_oob;
 273                nand->ecc.size = 512;
 274                nand->ecc.bytes = 3;
 275                nand->ecc.hwctl = omap_enable_hwecc;
 276                nand->ecc.correct = omap_correct_data;
 277                nand->ecc.calculate = omap_calculate_ecc;
 278                omap_hwecc_init(nand);
 279                printf("HW ECC selected\n");
 280        } else {
 281                nand->ecc.mode = NAND_ECC_SOFT;
 282                /* Use mtd default settings */
 283                nand->ecc.layout = NULL;
 284                printf("SW ECC selected\n");
 285        }
 286
 287        /* Update NAND handling after ECC mode switch */
 288        nand_scan_tail(mtd);
 289
 290        nand->options &= ~NAND_OWN_BUFFERS;
 291}
 292#endif /* CONFIG_SPL_BUILD */
 293
 294/*
 295 * Board-specific NAND initialization. The following members of the
 296 * argument are board-specific:
 297 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 298 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 299 * - cmd_ctrl: hardwarespecific function for accesing control-lines
 300 * - waitfunc: hardwarespecific function for accesing device ready/busy line
 301 * - ecc.hwctl: function to enable (reset) hardware ecc generator
 302 * - ecc.mode: mode of ecc, see defines
 303 * - chip_delay: chip dependent delay for transfering data from array to
 304 *   read regs (tR)
 305 * - options: various chip options. They can partly be set to inform
 306 *   nand_scan about special functionality. See the defines for further
 307 *   explanation
 308 */
 309int board_nand_init(struct nand_chip *nand)
 310{
 311        int32_t gpmc_config = 0;
 312        cs = 0;
 313
 314        /*
 315         * xloader/Uboot's gpmc configuration would have configured GPMC for
 316         * nand type of memory. The following logic scans and latches on to the
 317         * first CS with NAND type memory.
 318         * TBD: need to make this logic generic to handle multiple CS NAND
 319         * devices.
 320         */
 321        while (cs < GPMC_MAX_CS) {
 322                /* Check if NAND type is set */
 323                if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 324                        /* Found it!! */
 325                        break;
 326                }
 327                cs++;
 328        }
 329        if (cs >= GPMC_MAX_CS) {
 330                printf("NAND: Unable to find NAND settings in "
 331                        "GPMC Configuration - quitting\n");
 332                return -ENODEV;
 333        }
 334
 335        gpmc_config = readl(&gpmc_cfg->config);
 336        /* Disable Write protect */
 337        gpmc_config |= 0x10;
 338        writel(gpmc_config, &gpmc_cfg->config);
 339
 340        nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 341        nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 342
 343        nand->cmd_ctrl = omap_nand_hwcontrol;
 344        nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
 345        /* If we are 16 bit dev, our gpmc config tells us that */
 346        if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
 347                nand->options |= NAND_BUSWIDTH_16;
 348
 349        nand->chip_delay = 100;
 350        /* Default ECC mode */
 351#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
 352        nand->ecc.mode = NAND_ECC_SOFT;
 353#else
 354        nand->ecc.mode = NAND_ECC_HW;
 355        nand->ecc.layout = &hw_nand_oob;
 356        nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
 357        nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
 358        nand->ecc.hwctl = omap_enable_hwecc;
 359        nand->ecc.correct = omap_correct_data;
 360        nand->ecc.calculate = omap_calculate_ecc;
 361        omap_hwecc_init(nand);
 362#endif
 363
 364#ifdef CONFIG_SPL_BUILD
 365        if (nand->options & NAND_BUSWIDTH_16)
 366                nand->read_buf = nand_read_buf16;
 367        else
 368                nand->read_buf = nand_read_buf;
 369        nand->dev_ready = omap_spl_dev_ready;
 370#endif
 371
 372        return 0;
 373}
 374