LXR uboot/drivers/usb/gadget/regs-otg.h

   1/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
   2 *
   3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
   4 *
   5 * Registers remapping:
   6 * Lukasz Majewski <l.majewski@samsumg.com>
   7 *
   8 * This include file is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 */
  13
  14#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
  15#define __ASM_ARCH_REGS_USB_OTG_HS_H
  16
  17/* USB2.0 OTG Controller register */
  18struct s3c_usbotg_phy {
  19        u32 phypwr;
  20        u32 phyclk;
  21        u32 rstcon;
  22};
  23
  24/* Device Logical IN Endpoint-Specific Registers */
  25struct s3c_dev_in_endp {
  26        u32 diepctl;
  27        u8  res1[4];
  28        u32 diepint;
  29        u8  res2[4];
  30        u32 dieptsiz;
  31        u32 diepdma;
  32        u8  res3[4];
  33        u32 diepdmab;
  34};
  35
  36/* Device Logical OUT Endpoint-Specific Registers */
  37struct s3c_dev_out_endp {
  38        u32 doepctl;
  39        u8  res1[4];
  40        u32 doepint;
  41        u8  res2[4];
  42        u32 doeptsiz;
  43        u32 doepdma;
  44        u8  res3[4];
  45        u32 doepdmab;
  46};
  47
  48struct ep_fifo {
  49        u32 fifo;
  50        u8  res[4092];
  51};
  52
  53/* USB2.0 OTG Controller register */
  54struct s3c_usbotg_reg {
  55        /* Core Global Registers */
  56        u32 gotgctl; /* OTG Control & Status */
  57        u32 gotgint; /* OTG Interrupt */
  58        u32 gahbcfg; /* Core AHB Configuration */
  59        u32 gusbcfg; /* Core USB Configuration */
  60        u32 grstctl; /* Core Reset */
  61        u32 gintsts; /* Core Interrupt */
  62        u32 gintmsk; /* Core Interrupt Mask */
  63        u32 grxstsr; /* Receive Status Debug Read/Status Read */
  64        u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
  65        u32 grxfsiz; /* Receive FIFO Size */
  66        u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
  67        u8  res1[216];
  68        u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
  69        u8  res2[1728];
  70        /* Device Configuration */
  71        u32 dcfg; /* Device Configuration Register */
  72        u32 dctl; /* Device Control */
  73        u32 dsts; /* Device Status */
  74        u8  res3[4];
  75        u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
  76        u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
  77        u32 daint; /* Device All Endpoints Interrupt */
  78        u32 daintmsk; /* Device All Endpoints Interrupt Mask */
  79        u8  res4[224];
  80        struct s3c_dev_in_endp in_endp[16];
  81        struct s3c_dev_out_endp out_endp[16];
  82        u8  res5[768];
  83        struct ep_fifo ep[16];
  84};
  85
  86/*===================================================================== */
  87/*definitions related to CSR setting */
  88
  89/* S3C_UDC_OTG_GOTGCTL */
  90#define B_SESSION_VALID         (0x1<<19)
  91#define A_SESSION_VALID         (0x1<<18)
  92
  93/* S3C_UDC_OTG_GAHBCFG */
  94#define PTXFE_HALF                      (0<<8)
  95#define PTXFE_ZERO                      (1<<8)
  96#define NPTXFE_HALF                     (0<<7)
  97#define NPTXFE_ZERO                     (1<<7)
  98#define MODE_SLAVE                      (0<<5)
  99#define MODE_DMA                        (1<<5)
 100#define BURST_SINGLE                    (0<<1)
 101#define BURST_INCR                      (1<<1)
 102#define BURST_INCR4                     (3<<1)
 103#define BURST_INCR8                     (5<<1)
 104#define BURST_INCR16                    (7<<1)
 105#define GBL_INT_UNMASK                  (1<<0)
 106#define GBL_INT_MASK                    (0<<0)
 107
 108/* S3C_UDC_OTG_GRSTCTL */
 109#define AHB_MASTER_IDLE         (1u<<31)
 110#define CORE_SOFT_RESET         (0x1<<0)
 111
 112/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
 113#define INT_RESUME                      (1u<<31)
 114#define INT_DISCONN                     (0x1<<29)
 115#define INT_CONN_ID_STS_CNG             (0x1<<28)
 116#define INT_OUT_EP                      (0x1<<19)
 117#define INT_IN_EP                       (0x1<<18)
 118#define INT_ENUMDONE                    (0x1<<13)
 119#define INT_RESET                       (0x1<<12)
 120#define INT_SUSPEND                     (0x1<<11)
 121#define INT_EARLY_SUSPEND               (0x1<<10)
 122#define INT_NP_TX_FIFO_EMPTY            (0x1<<5)
 123#define INT_RX_FIFO_NOT_EMPTY           (0x1<<4)
 124#define INT_SOF                 (0x1<<3)
 125#define INT_DEV_MODE                    (0x0<<0)
 126#define INT_HOST_MODE                   (0x1<<1)
 127#define INT_GOUTNakEff                  (0x01<<7)
 128#define INT_GINNakEff                   (0x01<<6)
 129
 130#define FULL_SPEED_CONTROL_PKT_SIZE     8
 131#define FULL_SPEED_BULK_PKT_SIZE        64
 132
 133#define HIGH_SPEED_CONTROL_PKT_SIZE     64
 134#define HIGH_SPEED_BULK_PKT_SIZE        512
 135
 136#define RX_FIFO_SIZE                    (1024*4)
 137#define NPTX_FIFO_SIZE                  (1024*4)
 138#define PTX_FIFO_SIZE                   (1536*1)
 139
 140#define DEPCTL_TXFNUM_0         (0x0<<22)
 141#define DEPCTL_TXFNUM_1         (0x1<<22)
 142#define DEPCTL_TXFNUM_2         (0x2<<22)
 143#define DEPCTL_TXFNUM_3         (0x3<<22)
 144#define DEPCTL_TXFNUM_4         (0x4<<22)
 145
 146/* Enumeration speed */
 147#define USB_HIGH_30_60MHZ               (0x0<<1)
 148#define USB_FULL_30_60MHZ               (0x1<<1)
 149#define USB_LOW_6MHZ                    (0x2<<1)
 150#define USB_FULL_48MHZ                  (0x3<<1)
 151
 152/* S3C_UDC_OTG_GRXSTSP STATUS */
 153#define OUT_PKT_RECEIVED                (0x2<<17)
 154#define OUT_TRANSFER_COMPLELTED (0x3<<17)
 155#define SETUP_TRANSACTION_COMPLETED     (0x4<<17)
 156#define SETUP_PKT_RECEIVED              (0x6<<17)
 157#define GLOBAL_OUT_NAK                  (0x1<<17)
 158
 159/* S3C_UDC_OTG_DCTL device control register */
 160#define NORMAL_OPERATION                (0x1<<0)
 161#define SOFT_DISCONNECT         (0x1<<1)
 162
 163/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
 164#define DAINT_OUT_BIT                   (16)
 165#define DAINT_MASK                      (0xFFFF)
 166
 167/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
 168   control IN/OUT endpoint 0 control register */
 169#define DEPCTL_EPENA                    (0x1<<31)
 170#define DEPCTL_EPDIS                    (0x1<<30)
 171#define DEPCTL_SETD1PID         (0x1<<29)
 172#define DEPCTL_SETD0PID         (0x1<<28)
 173#define DEPCTL_SNAK                     (0x1<<27)
 174#define DEPCTL_CNAK                     (0x1<<26)
 175#define DEPCTL_STALL                    (0x1<<21)
 176#define DEPCTL_TYPE_BIT         (18)
 177#define DEPCTL_TYPE_MASK                (0x3<<18)
 178#define DEPCTL_CTRL_TYPE                (0x0<<18)
 179#define DEPCTL_ISO_TYPE         (0x1<<18)
 180#define DEPCTL_BULK_TYPE                (0x2<<18)
 181#define DEPCTL_INTR_TYPE                (0x3<<18)
 182#define DEPCTL_USBACTEP         (0x1<<15)
 183#define DEPCTL_NEXT_EP_BIT              (11)
 184#define DEPCTL_MPS_BIT                  (0)
 185#define DEPCTL_MPS_MASK         (0x7FF)
 186
 187#define DEPCTL0_MPS_64                  (0x0<<0)
 188#define DEPCTL0_MPS_32                  (0x1<<0)
 189#define DEPCTL0_MPS_16                  (0x2<<0)
 190#define DEPCTL0_MPS_8                   (0x3<<0)
 191#define DEPCTL_MPS_BULK_512             (512<<0)
 192#define DEPCTL_MPS_INT_MPS_16           (16<<0)
 193
 194#define DIEPCTL0_NEXT_EP_BIT            (11)
 195
 196
 197/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
 198   common interrupt mask register */
 199/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
 200#define BACK2BACK_SETUP_RECEIVED        (0x1<<6)
 201#define INTKNEPMIS                      (0x1<<5)
 202#define INTKN_TXFEMP                    (0x1<<4)
 203#define NON_ISO_IN_EP_TIMEOUT           (0x1<<3)
 204#define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
 205#define AHB_ERROR                       (0x1<<2)
 206#define EPDISBLD                        (0x1<<1)
 207#define TRANSFER_DONE                   (0x1<<0)
 208
 209#define USB_PHY_CTRL_EN0                (0x1 << 0)
 210
 211/* OPHYPWR */
 212#define PHY_0_SLEEP                     (0x1 << 5)
 213#define OTG_DISABLE_0                   (0x1 << 4)
 214#define ANALOG_PWRDOWN                  (0x1 << 3)
 215#define FORCE_SUSPEND_0                 (0x1 << 0)
 216
 217/* URSTCON */
 218#define HOST_SW_RST                     (0x1 << 4)
 219#define PHY_SW_RST1                     (0x1 << 3)
 220#define PHYLNK_SW_RST                   (0x1 << 2)
 221#define LINK_SW_RST                     (0x1 << 1)
 222#define PHY_SW_RST0                     (0x1 << 0)
 223
 224/* OPHYCLK */
 225#define COMMON_ON_N1                    (0x1 << 7)
 226#define COMMON_ON_N0                    (0x1 << 4)
 227#define ID_PULLUP0                      (0x1 << 2)
 228#define CLK_SEL_24MHZ                   (0x3 << 0)
 229#define CLK_SEL_12MHZ                   (0x2 << 0)
 230#define CLK_SEL_48MHZ                   (0x0 << 0)
 231
 232/* Device Configuration Register DCFG */
 233#define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
 234#define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
 235#define DEV_SPEED_LOW_SPEED_11          (0x2 << 0)
 236#define DEV_SPEED_FULL_SPEED_11         (0x3 << 0)
 237#define EP_MISS_CNT(x)                  (x << 18)
 238#define DEVICE_ADDRESS(x)               (x << 4)
 239
 240/* Core Reset Register (GRSTCTL) */
 241#define TX_FIFO_FLUSH                   (0x1 << 5)
 242#define RX_FIFO_FLUSH                   (0x1 << 4)
 243#define TX_FIFO_NUMBER(x)               (x << 6)
 244#define TX_FIFO_FLUSH_ALL               TX_FIFO_NUMBER(0x10)
 245
 246/* Masks definitions */
 247#define GINTMSK_INIT    (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
 248                        | INT_RESET | INT_SUSPEND)
 249#define DOEPMSK_INIT    (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
 250#define DIEPMSK_INIT    (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
 251#define GAHBCFG_INIT    (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
 252                        | GBL_INT_UNMASK)
 253
 254/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
 255#define DIEPT_SIZ_PKT_CNT(x)                      (x << 19)
 256#define DIEPT_SIZ_XFER_SIZE(x)                    (x << 0)
 257
 258/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
 259#define DOEPT_SIZ_PKT_CNT(x)                      (x << 19)
 260#define DOEPT_SIZ_XFER_SIZE(x)                    (x << 0)
 261#define DOEPT_SIZ_XFER_SIZE_MAX_EP0               (0x7F << 0)
 262#define DOEPT_SIZ_XFER_SIZE_MAX_EP                (0x7FFF << 0)
 263
 264/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
 265#define DIEPCTL_TX_FIFO_NUM(x)                    (x << 22)
 266#define DIEPCTL_TX_FIFO_NUM_MASK                  (~DIEPCTL_TX_FIFO_NUM(0xF))
 267
 268/* Device ALL Endpoints Interrupt Register (DAINT) */
 269#define DAINT_IN_EP_INT(x)                        (x << 0)
 270#define DAINT_OUT_EP_INT(x)                       (x << 16)
 271#endif
 272