1/* 2 * (C) Copyright 2001 3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* This define must be before the core.h include */ 32#define CONFIG_DB64460 1 /* this is an DB64460 board */ 33 34#ifndef __ASSEMBLY__ 35#include "../board/Marvell/include/core.h" 36#endif 37 38/*-----------------------------------------------------*/ 39/* #include "../board/db64460/local.h" */ 40#ifndef __LOCAL_H 41#define __LOCAL_H 42 43#define CONFIG_ETHADDR 64:46:00:00:00:01 44#define CONFIG_HAS_ETH1 45#define CONFIG_ETH1ADDR 64:46:00:00:00:02 46#define CONFIG_HAS_ETH2 47#define CONFIG_ETH2ADDR 64:46:00:00:00:03 48 49#define CONFIG_ENV_OVERWRITE 50#endif /* __CONFIG_H */ 51 52/* 53 * High Level Configuration Options 54 * (easy to change) 55 */ 56 57#define CONFIG_74xx /* we have a 750FX (override local.h) */ 58 59#define CONFIG_DB64460 1 /* this is an DB64460 board */ 60 61#define CONFIG_SYS_TEXT_BASE 0xfff00000 62 63#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ 64/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the 65 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. 66 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, 67 see sdram_init.c */ 68#undef CONFIG_ECC /* enable ECC support */ 69#define CONFIG_MV64460_ECC 70 71/* which initialization functions to call for this board */ 72#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ 73#define CONFIG_BOARD_EARLY_INIT_F 74 75#define CONFIG_SYS_BOARD_NAME "DB64460" 76#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" 77 78/*#define CONFIG_SYS_HUSH_PARSER */ 79#undef CONFIG_SYS_HUSH_PARSER 80 81#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 82 83/* 84 * The following defines let you select what serial you want to use 85 * for your console driver. 86 * 87 * what to do: 88 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial 89 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 90 * to 0 below. 91 * 92 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another 93 * mpsc channel, change CONFIG_MPSC_PORT to the desired value. 94 */ 95 96#define CONFIG_MPSC_PORT 0 97 98/* to change the default ethernet port, use this define (options: 0, 1, 2) */ 99#define MV_ETH_DEVS 3 100 101/* #undef CONFIG_ETHER_PORT_MII */ 102#if 0 103#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 104#else 105#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 106#endif 107#define CONFIG_ZERO_BOOTDELAY_CHECK 108 109 110#undef CONFIG_BOOTARGS 111/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ 112 113/* ronen - autoboot using tftp */ 114#if (CONFIG_BOOTDELAY >= 0) 115#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ 116 setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ 117 ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " 118 119#define CONFIG_BOOTARGS "console=ttyS0,115200" 120 121#endif 122 123/* ronen - the u-boot.bin should be ~0x30000 bytes */ 124#define CONFIG_EXTRA_ENV_SETTINGS \ 125 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ 126cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ 127 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ 128cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ 129 "bootargs_root=root=/dev/nfs rw\0" \ 130 "bootargs_end=:::DB64460:eth0:none \0"\ 131 "ethprime=mv_enet0\0"\ 132 "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ 133ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" 134 135/* --------------------------------------------------------------------------------------------------------------- */ 136/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ 137 138#define CONFIG_IPADDR 10.2.40.90 139 140#define CONFIG_SERIAL "No. 1" 141#define CONFIG_SERVERIP 10.2.1.126 142#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" 143 144 145#define CONFIG_TESTDRAMDATA y 146#define CONFIG_TESTDRAMADDRESS n 147#define CONFIG_TESETDRAMWALK n 148 149/* --------------------------------------------------------------------------------------------------------------- */ 150 151#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 152#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ 153 154#undef CONFIG_WATCHDOG /* watchdog disabled */ 155#undef CONFIG_ALTIVEC /* undef to disable */ 156 157/* 158 * BOOTP options 159 */ 160#define CONFIG_BOOTP_SUBNETMASK 161#define CONFIG_BOOTP_GATEWAY 162#define CONFIG_BOOTP_HOSTNAME 163#define CONFIG_BOOTP_BOOTPATH 164#define CONFIG_BOOTP_BOOTFILESIZE 165 166 167/* 168 * JFFS2 partitions 169 * 170 */ 171/* No command line, one static partition, whole device */ 172#undef CONFIG_CMD_MTDPARTS 173#define CONFIG_JFFS2_DEV "nor1" 174#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 175#define CONFIG_JFFS2_PART_OFFSET 0x00000000 176 177/* mtdparts command line support */ 178 179/* Use first bank for JFFS2, second bank contains U-Boot. 180 * 181 * Note: fake mtd_id's used, no linux mtd map file. 182 */ 183/* 184#define CONFIG_CMD_MTDPARTS 185#define MTDIDS_DEFAULT "nor1=db64460-1" 186#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" 187*/ 188 189 190/* 191 * Command line configuration. 192 */ 193#include <config_cmd_default.h> 194 195#define CONFIG_CMD_ASKENV 196#define CONFIG_CMD_I2C 197#define CONFIG_CMD_EEPROM 198#define CONFIG_CMD_CACHE 199#define CONFIG_CMD_JFFS2 200#define CONFIG_CMD_PCI 201#define CONFIG_CMD_NET 202 203 204/* 205 * Miscellaneous configurable options 206 */ 207#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 208#define CONFIG_SYS_I2C_MULTI_EEPROMS 209#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ 210 211/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ 212#define CONFIG_SYS_LONGHELP /* undef to save memory */ 213#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 214#if defined(CONFIG_CMD_KGDB) 215#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 216#else 217#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 218#endif 219#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 220#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 221#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 222 223/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ 224/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ 225/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ 226 227/* 228#define CONFIG_SYS_DRAM_TEST 229 * DRAM tests 230 * CONFIG_SYS_DRAM_TEST - enables the following tests. 231 * 232 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines 233 * Environment variable 'test_dram_data' must be 234 * set to 'y'. 235 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely 236 * addressable. Environment variable 237 * 'test_dram_address' must be set to 'y'. 238 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. 239 * This test takes about 6 minutes to test 64 MB. 240 * Environment variable 'test_dram_walk' must be 241 * set to 'y'. 242 */ 243#define CONFIG_SYS_DRAM_TEST 244#if defined(CONFIG_SYS_DRAM_TEST) 245#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 246/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ 247#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ 248#define CONFIG_SYS_DRAM_TEST_DATA 249#define CONFIG_SYS_DRAM_TEST_ADDRESS 250#define CONFIG_SYS_DRAM_TEST_WALK 251#endif /* CONFIG_SYS_DRAM_TEST */ 252 253#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ 254#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ 255 256#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ 257 258#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 259/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ 260#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ 261 262#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ 263#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ 264 265/*ronen - this is the Tclk (MV64460 core) */ 266#define CONFIG_SYS_TCLK 133000000 267 268 269#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 270 271#define CONFIG_SYS_750FX_HID0 0x8000c084 272#define CONFIG_SYS_750FX_HID1 0x54800000 273#define CONFIG_SYS_750FX_HID2 0x00000000 274 275/* 276 * Low Level Configuration Settings 277 * (address mappings, register initial values, etc.) 278 * You should know what you are doing if you make changes here. 279 */ 280 281/*----------------------------------------------------------------------- 282 * Definitions for initial stack pointer and data area 283 */ 284 285/* 286 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS 287 * To an unused memory region. The stack will remain in cache until RAM 288 * is initialized 289*/ 290#define CONFIG_SYS_INIT_RAM_LOCK 291#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ 292#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 293#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 294 295#define RELOCATE_INTERNAL_RAM_ADDR 296#ifdef RELOCATE_INTERNAL_RAM_ADDR 297 #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 298#endif 299 300/*----------------------------------------------------------------------- 301 * Start addresses for the final memory configuration 302 * (Set up by the startup code) 303 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 304 */ 305#define CONFIG_SYS_SDRAM_BASE 0x00000000 306/* Dummies for BAT 4-7 */ 307#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ 308#define CONFIG_SYS_SDRAM2_BASE 0x20000000 309#define CONFIG_SYS_SDRAM3_BASE 0x30000000 310#define CONFIG_SYS_SDRAM4_BASE 0x40000000 311#define CONFIG_SYS_FLASH_BASE 0xfff00000 312 313#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 314#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ 315 316#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ 317#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ 318#define PCI0_IO_BASE_BOOTM 0xfd000000 319 320#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 321#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 322#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 323#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ 324 325/* areas to map different things with the GT in physical space */ 326#define CONFIG_SYS_DRAM_BANKS 4 327 328/* What to put in the bats. */ 329#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 330 331/* Peripheral Device section */ 332 333/*******************************************************/ 334/* We have on the db64460 Board : */ 335/* GT-Chipset Register Area */ 336/* GT-Chipset internal SRAM 256k */ 337/* SRAM on external device module */ 338/* Real time clock on external device module */ 339/* dobble UART on external device module */ 340/* Data flash on external device module */ 341/* Boot flash on external device module */ 342/*******************************************************/ 343#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ 344#define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ 345 346/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 347#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ 348#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ 349 350#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ 351#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ 352#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ 353#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ 354 355#define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ 356#define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ 357#define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ 358#define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ 359/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 360 361/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ 362#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ 363#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ 364#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ 365#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ 366#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ 367 368 /* c 4 a 8 2 4 1 c */ 369 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ 370 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ 371 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ 372 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ 373 374 375/* ronen - update MPP Control MV64460*/ 376#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 377#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 378#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 379#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 380 381/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ 382 383 384# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ 385 /* gpp[31] gpp[30] gpp[29] gpp[28] */ 386 /* gpp[27] gpp[24]*/ 387 /* gpp[19:14] */ 388 389/* setup new config_value for MV64460 DDR-RAM !! */ 390# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ 391 392#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE 393#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ 394#define CONFIG_SYS_INIT_CHAN1 395#define CONFIG_SYS_INIT_CHAN2 396 397#define SRAM_BASE CONFIG_SYS_DEV0_SPACE 398#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ 399 400 401/*----------------------------------------------------------------------- 402 * PCI stuff 403 *----------------------------------------------------------------------- 404 */ 405 406#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 407#define PCI_HOST_FORCE 1 /* configure as pci host */ 408#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 409 410#define CONFIG_PCI /* include pci support */ 411#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 412#define CONFIG_PCI_PNP /* do pci plug-and-play */ 413#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ 414 415/* PCI MEMORY MAP section */ 416#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 417#define CONFIG_SYS_PCI0_MEM_SIZE _128M 418#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 419#define CONFIG_SYS_PCI1_MEM_SIZE _128M 420 421#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) 422#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) 423 424/* PCI I/O MAP section */ 425#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 426#define CONFIG_SYS_PCI0_IO_SIZE _16M 427#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 428#define CONFIG_SYS_PCI1_IO_SIZE _16M 429 430#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) 431#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ 432#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) 433#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ 434 435#if defined (CONFIG_750CX) 436#define CONFIG_SYS_PCI_IDSEL 0x0 437#else 438#define CONFIG_SYS_PCI_IDSEL 0x30 439#endif 440/*---------------------------------------------------------------------- 441 * Initial BAT mappings 442 */ 443 444/* NOTES: 445 * 1) GUARDED and WRITE_THRU not allowed in IBATS 446 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT 447 */ 448 449/* SDRAM */ 450#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 451#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 452#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 453#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 454 455/* init ram */ 456#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 457#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) 458#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 459#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 460 461/* PCI0, PCI1 in one BAT */ 462#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS 463#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 464#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 465#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 466 467/* GT regs, bootrom, all the devices, PCI I/O */ 468#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) 469#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) 470#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 471#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 472 473/* I2C addresses for the two DIMM SPD chips */ 474#define DIMM0_I2C_ADDR 0x56 475#define DIMM1_I2C_ADDR 0x54 476 477/* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 8 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ 483 484/*----------------------------------------------------------------------- 485 * FLASH organization 486 */ 487#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 488#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 489 490#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ 491#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ 492#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ 493 494#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 495#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 496#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ 497#define CONFIG_SYS_FLASH_CFI 1 498 499#define CONFIG_ENV_IS_IN_FLASH 1 500#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 501#define CONFIG_ENV_SECT_SIZE 0x10000 502#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ 503/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ 504 505/*----------------------------------------------------------------------- 506 * Cache Configuration 507 */ 508#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 509#if defined(CONFIG_CMD_KGDB) 510#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 511#endif 512 513/*----------------------------------------------------------------------- 514 * L2CR setup -- make sure this is right for your board! 515 * look in include/mpc74xx.h for the defines used here 516 */ 517 518#define CONFIG_SYS_L2 519 520 521#if defined (CONFIG_750CX) || defined (CONFIG_750FX) 522#define L2_INIT 0 523#else 524 525#define L2_INIT 0 526/* 527#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 528 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 529*/ 530#endif 531 532#define L2_ENABLE (L2_INIT | L2CR_L2E) 533 534#define CONFIG_SYS_BOARD_ASM_INIT 1 535 536#endif /* __CONFIG_H */ 537