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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38
39
40
41
42#define CONFIG_405EP 1
43#define CONFIG_4xx 1
44#define CONFIG_HH405 1
45
46#define CONFIG_SYS_TEXT_BASE 0xFFF80000
47
48#define CONFIG_BOARD_EARLY_INIT_F 1
49#define CONFIG_MISC_INIT_R 1
50
51#define CONFIG_SYS_CLK_FREQ 33333400
52
53#define CONFIG_BOARD_TYPES 1
54
55#define CONFIG_BAUDRATE 9600
56#define CONFIG_BOOTDELAY 3
57
58#undef CONFIG_BOOTARGS
59#undef CONFIG_BOOTCOMMAND
60
61#define CONFIG_PREBOOT "autoupd"
62
63#define CONFIG_EXTRA_ENV_SETTINGS \
64 "pciconfighost=1\0" \
65 ""
66
67#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
68
69#define CONFIG_PPC4xx_EMAC
70#undef CONFIG_HAS_ETH1
71
72#define CONFIG_MII 1
73#define CONFIG_PHY_ADDR 0
74#define CONFIG_LXT971_NO_SLEEP 1
75#define CONFIG_RESET_PHY_R 1
76
77#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
78
79
80
81
82#define CONFIG_VIDEO
83
84#ifdef CONFIG_VIDEO
85#define CONFIG_VIDEO_SM501
86#if 0
87#define CONFIG_VIDEO_SM501_32BPP
88#else
89#define CONFIG_VIDEO_SM501_16BPP
90#endif
91#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
92#define CONFIG_CFB_CONSOLE
93#define CONFIG_VIDEO_LOGO
94#define CONFIG_VGA_AS_SINGLE_DEVICE
95#define CONFIG_CONSOLE_EXTRA_INFO
96#define CONFIG_VIDEO_SW_CURSOR
97#define CONFIG_SPLASH_SCREEN
98#define CONFIG_SYS_CONSOLE_IS_IN_ENV
99#define CONFIG_SPLASH_SCREEN
100#define CONFIG_VIDEO_BMP_GZIP
101#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
102
103#endif
104
105
106
107
108
109#define CONFIG_BOOTP_BOOTFILESIZE
110#define CONFIG_BOOTP_BOOTPATH
111#define CONFIG_BOOTP_GATEWAY
112#define CONFIG_BOOTP_HOSTNAME
113
114
115
116
117
118#include <config_cmd_default.h>
119
120#define CONFIG_CMD_DHCP
121#define CONFIG_CMD_PCI
122#define CONFIG_CMD_IRQ
123#define CONFIG_CMD_IDE
124#define CONFIG_CMD_FAT
125#define CONFIG_CMD_EXT2
126#define CONFIG_CMD_ELF
127#define CONFIG_CMD_NAND
128#define CONFIG_CMD_I2C
129#define CONFIG_CMD_DATE
130#define CONFIG_CMD_MII
131#define CONFIG_CMD_PING
132#define CONFIG_CMD_EEPROM
133
134#ifdef CONFIG_VIDEO
135#define CONFIG_CMD_BMP
136#endif
137
138#define CONFIG_MAC_PARTITION
139#define CONFIG_DOS_PARTITION
140
141#define CONFIG_SUPPORT_VFAT
142
143#define CONFIG_AUTO_UPDATE 1
144#undef CONFIG_AUTO_UPDATE_SHOW
145
146#undef CONFIG_BZIP2
147#undef CONFIG_WATCHDOG
148
149#define CONFIG_SDRAM_BANK0 1
150
151
152
153
154#define CONFIG_SYS_LONGHELP
155#define CONFIG_SYS_PROMPT "=> "
156
157#undef CONFIG_SYS_HUSH_PARSER
158#ifdef CONFIG_SYS_HUSH_PARSER
159#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
160#endif
161
162#if defined(CONFIG_CMD_KGDB)
163#define CONFIG_SYS_CBSIZE 1024
164#else
165#define CONFIG_SYS_CBSIZE 256
166#endif
167#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
168#define CONFIG_SYS_MAXARGS 16
169#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
170
171#define CONFIG_SYS_DEVICE_NULLDEV 1
172
173#undef CONFIG_SYS_CONSOLE_INFO_QUIET
174
175#define CONFIG_AUTO_COMPLETE 1
176
177#define CONFIG_SYS_MEMTEST_START 0x0400000
178#define CONFIG_SYS_MEMTEST_END 0x0C00000
179
180#define CONFIG_CONS_INDEX 2
181#define CONFIG_SYS_NS16550
182#define CONFIG_SYS_NS16550_SERIAL
183#define CONFIG_SYS_NS16550_REG_SIZE 1
184#define CONFIG_SYS_NS16550_CLK get_serial_clock()
185
186#undef CONFIG_SYS_EXT_SERIAL_CLOCK
187#define CONFIG_SYS_BASE_BAUD 691200
188
189
190#define CONFIG_SYS_BAUDRATE_TABLE \
191 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
192 57600, 115200, 230400, 460800, 921600 }
193
194#define CONFIG_SYS_LOAD_ADDR 0x100000
195#define CONFIG_SYS_EXTBDINFO 1
196
197#define CONFIG_SYS_HZ 1000
198
199#define CONFIG_ZERO_BOOTDELAY_CHECK
200
201#define CONFIG_VERSION_VARIABLE 1
202
203#define CONFIG_SYS_RX_ETH_BUFFER 16
204
205
206
207
208
209#define CONFIG_RTC_DS1338
210#define CONFIG_SYS_I2C_RTC_ADDR 0x68
211
212
213
214
215
216#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
217#define CONFIG_SYS_MAX_NAND_DEVICE 1
218#define NAND_BIG_DELAY_US 25
219
220#define CONFIG_SYS_NAND_CE (0x80000000 >> 1)
221#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)
222#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)
223#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)
224
225#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1
226#define CONFIG_SYS_NAND_QUIET 1
227
228
229
230
231
232#define PCI_HOST_ADAPTER 0
233#define PCI_HOST_FORCE 1
234#define PCI_HOST_AUTO 2
235
236#define CONFIG_PCI
237#define CONFIG_PCI_HOST PCI_HOST_HOST
238#define CONFIG_PCI_PNP
239
240
241#define CONFIG_PCI_SCAN_SHOW
242
243#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
244
245#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
246#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
247#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
248#define CONFIG_SYS_PCI_PTM1LA 0x00000000
249#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
250#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
251#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
252#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
253#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
254
255
256
257
258
259#undef CONFIG_IDE_8xx_DIRECT
260#undef CONFIG_IDE_LED
261#define CONFIG_IDE_RESET 1
262
263#define CONFIG_SYS_IDE_MAXBUS 1
264#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
265
266#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
267#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
268
269#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
270#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
271#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
272
273
274
275
276
277
278#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
279
280
281
282#define FLASH_BASE0_PRELIM 0xFFC00000
283
284#define CONFIG_SYS_MAX_FLASH_BANKS 1
285#define CONFIG_SYS_MAX_FLASH_SECT 256
286
287#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
288#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
289
290#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
291#define CONFIG_SYS_FLASH_ADDR0 0x5555
292#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
293
294
295
296
297#define CONFIG_SYS_FLASH_READ0 0x0000
298#define CONFIG_SYS_FLASH_READ1 0x0001
299#define CONFIG_SYS_FLASH_READ2 0x0002
300
301#define CONFIG_SYS_FLASH_EMPTY_INFO
302
303#if 0
304#define CONFIG_SYS_JFFS2_FIRST_BANK 0
305#define CONFIG_SYS_JFFS2_NUM_BANKS 1
306#endif
307
308
309
310
311
312
313#define CONFIG_SYS_SDRAM_BASE 0x00000000
314#define CONFIG_SYS_FLASH_BASE 0xFFF80000
315#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
316#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
317#define CONFIG_SYS_MALLOC_LEN (4 << 20)
318
319#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
320# define CONFIG_SYS_RAMBOOT 1
321#else
322# undef CONFIG_SYS_RAMBOOT
323#endif
324
325
326
327
328#define CONFIG_ENV_IS_IN_EEPROM 1
329#define CONFIG_ENV_OFFSET 0x100
330#define CONFIG_ENV_SIZE 0x700
331
332
333#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000
334#define CONFIG_SYS_NVRAM_SIZE 0x8000
335
336
337
338
339#define CONFIG_HARD_I2C
340#define CONFIG_PPC4XX_I2C
341#if 0
342#define CONFIG_SYS_I2C_SPEED 400000
343#else
344#define CONFIG_SYS_I2C_SPEED 100000
345#endif
346#define CONFIG_SYS_I2C_SLAVE 0x7F
347
348#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
349#define CONFIG_SYS_EEPROM_WREN 1
350
351#if 1
352
353#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
354
355#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
356#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
357
358
359#else
360
361#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
362
363#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
364#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
365
366
367#endif
368#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
369
370
371
372
373
374#define CAN_BA 0xF0000000
375#define LCD_BA 0xF1000000
376#define CONFIG_SYS_NAND_BASE 0xF4000000
377#define CONFIG_SYS_NVRAM_BASE 0xF4080000
378
379
380#define CONFIG_SYS_EBC_PB0AP 0x92015480
381#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
382
383
384#define CONFIG_SYS_EBC_PB1AP 0x92015480
385#define CONFIG_SYS_EBC_PB1CR 0xF4018000
386
387
388#define CONFIG_SYS_EBC_PB2AP 0x010053C0
389#define CONFIG_SYS_EBC_PB2CR 0xF0018000
390
391
392#define CONFIG_SYS_EBC_PB3AP 0x010053C0
393#define CONFIG_SYS_EBC_PB3CR 0xF011A000
394
395
396#define CONFIG_SYS_EBC_PB4AP 0x03805380
397#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000
398
399
400
401
402
403#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000
404#define CONFIG_SYS_LCD_BIG_REG 0xF1000000
405#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000
406#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0
407
408
409
410
411
412
413
414
415#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
416
417
418
419
420
421#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100
422
423#define LCD_CLK_OFF 0x0000
424#define LCD_CLK_02083 0x1000
425#define LCD_CLK_03135 0x2000
426#define LCD_CLK_04165 0x3000
427#define LCD_CLK_06250 0x4000
428#define LCD_CLK_08330 0x5000
429#define LCD_CLK_12500 0x6000
430#define LCD_CLK_25000 0x7000
431
432#define CONFIG_SYS_FPGA_SPARTAN2 1
433#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
434
435
436#define CONFIG_SYS_FPGA_PRG 0x04000000
437#define CONFIG_SYS_FPGA_CLK 0x02000000
438#define CONFIG_SYS_FPGA_DATA 0x01000000
439#define CONFIG_SYS_FPGA_INIT 0x00010000
440#define CONFIG_SYS_FPGA_DONE 0x00008000
441
442
443
444
445
446#define CONFIG_SYS_TEMP_STACK_OCM 1
447
448
449#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
450#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
451#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
452#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
453
454#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
455#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
456
457
458
459
460
461
462
463
464
465
466
467
468
469#define CONFIG_SYS_GPIO0_OSRL 0x40000550
470#define CONFIG_SYS_GPIO0_OSRH 0x00000110
471#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
472#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
473#define CONFIG_SYS_GPIO0_TSRL 0x00000000
474#define CONFIG_SYS_GPIO0_TSRH 0x00000000
475#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
476
477#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
478#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8)
479#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9)
480#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
481#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
482
483
484
485
486
487#if 0
488#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
489#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
490#endif
491#if 0
492#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
493#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
494#endif
495#if 1
496#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
497#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
498#endif
499
500#endif
501