1/* 2 * Configuation settings for the Freescale MCF54451 EVB board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _M54451EVB_H 31#define _M54451EVB_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MCF5445x /* define processor family */ 38#define CONFIG_M54451 /* define processor type */ 39#define CONFIG_M54451EVB /* M54451EVB board */ 40 41#define CONFIG_MCFUART 42#define CONFIG_SYS_UART_PORT (0) 43#define CONFIG_BAUDRATE 115200 44#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 45 46#undef CONFIG_WATCHDOG 47 48#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 50/* 51 * BOOTP options 52 */ 53#define CONFIG_BOOTP_BOOTFILESIZE 54#define CONFIG_BOOTP_BOOTPATH 55#define CONFIG_BOOTP_GATEWAY 56#define CONFIG_BOOTP_HOSTNAME 57 58/* Command line configuration */ 59#include <config_cmd_default.h> 60 61#define CONFIG_CMD_BOOTD 62#define CONFIG_CMD_CACHE 63#define CONFIG_CMD_DATE 64#define CONFIG_CMD_DHCP 65#define CONFIG_CMD_ELF 66#define CONFIG_CMD_FLASH 67#define CONFIG_CMD_I2C 68#undef CONFIG_CMD_JFFS2 69#define CONFIG_CMD_MEMORY 70#define CONFIG_CMD_MISC 71#define CONFIG_CMD_MII 72#define CONFIG_CMD_NET 73#define CONFIG_CMD_NFS 74#define CONFIG_CMD_PING 75#define CONFIG_CMD_REGINFO 76#define CONFIG_CMD_SPI 77#define CONFIG_CMD_SF 78 79#undef CONFIG_CMD_LOADB 80#undef CONFIG_CMD_LOADS 81 82/* Network configuration */ 83#define CONFIG_MCFFEC 84#ifdef CONFIG_MCFFEC 85# define CONFIG_MII 1 86# define CONFIG_MII_INIT 1 87# define CONFIG_SYS_DISCOVER_PHY 88# define CONFIG_SYS_RX_ETH_BUFFER 8 89# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 90 91# define CONFIG_SYS_FEC0_PINMUX 0 92# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 93# define MCFFEC_TOUT_LOOP 50000 94 95# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 96# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" 97# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 98# define CONFIG_ETHPRIME "FEC0" 99# define CONFIG_IPADDR 192.162.1.2 100# define CONFIG_NETMASK 255.255.255.0 101# define CONFIG_SERVERIP 192.162.1.1 102# define CONFIG_GATEWAYIP 192.162.1.1 103# define CONFIG_OVERWRITE_ETHADDR_ONCE 104 105/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 106# ifndef CONFIG_SYS_DISCOVER_PHY 107# define FECDUPLEX FULL 108# define FECSPEED _100BASET 109# else 110# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 111# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 112# endif 113# endif /* CONFIG_SYS_DISCOVER_PHY */ 114#endif 115 116#define CONFIG_HOSTNAME M54451EVB 117#ifdef CONFIG_SYS_STMICRO_BOOT 118/* ST Micro serial flash */ 119#define CONFIG_SYS_LOAD_ADDR2 0x40010007 120#define CONFIG_EXTRA_ENV_SETTINGS \ 121 "netdev=eth0\0" \ 122 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 123 "loadaddr=0x40010000\0" \ 124 "sbfhdr=sbfhdr.bin\0" \ 125 "uboot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr} ${sbfhdr};" \ 127 "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 128 "upd=run load; run prog\0" \ 129 "prog=sf probe 0:1 1000000 3;" \ 130 "sf erase 0 30000;" \ 131 "sf write ${loadaddr} 0 30000;" \ 132 "save\0" \ 133 "" 134#else 135#define CONFIG_SYS_UBOOT_END 0x3FFFF 136#define CONFIG_EXTRA_ENV_SETTINGS \ 137 "netdev=eth0\0" \ 138 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 139 "loadaddr=40010000\0" \ 140 "u-boot=u-boot.bin\0" \ 141 "load=tftp ${loadaddr) ${u-boot}\0" \ 142 "upd=run load; run prog\0" \ 143 "prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \ 144 "; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \ 145 "cp.b ${loadaddr} 0 ${filesize};" \ 146 "save\0" \ 147 "" 148#endif 149 150/* Realtime clock */ 151#define CONFIG_MCFRTC 152#undef RTC_DEBUG 153#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 154 155/* Timer */ 156#define CONFIG_MCFTMR 157#undef CONFIG_MCFPIT 158 159/* I2c */ 160#define CONFIG_FSL_I2C 161#define CONFIG_HARD_I2C /* I2C with hardware support */ 162#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 163#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */ 164#define CONFIG_SYS_I2C_SLAVE 0x7F 165#define CONFIG_SYS_I2C_OFFSET 0x58000 166#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 167 168/* DSPI and Serial Flash */ 169#define CONFIG_CF_SPI 170#define CONFIG_CF_DSPI 171#define CONFIG_SERIAL_FLASH 172#define CONFIG_HARD_SPI 173#define CONFIG_SYS_SBFHDR_SIZE 0x7 174#ifdef CONFIG_CMD_SPI 175# define CONFIG_SPI_FLASH 176# define CONFIG_SPI_FLASH_STMICRO 177 178# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 179 DSPI_CTAR_PCSSCK_1CLK | \ 180 DSPI_CTAR_PASC(0) | \ 181 DSPI_CTAR_PDT(0) | \ 182 DSPI_CTAR_CSSCK(0) | \ 183 DSPI_CTAR_ASC(0) | \ 184 DSPI_CTAR_DT(1)) 185# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 186# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 187#endif 188 189/* Input, PCI, Flexbus, and VCO */ 190#define CONFIG_EXTRA_CLOCK 191 192#define CONFIG_PRAM 2048 /* 2048 KB */ 193 194#define CONFIG_SYS_PROMPT "-> " 195#define CONFIG_SYS_LONGHELP /* undef to save memory */ 196 197#if defined(CONFIG_CMD_KGDB) 198#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 199#else 200#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 201#endif 202#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 203#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 204#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 205 206#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 207 208#define CONFIG_SYS_HZ 1000 209 210#define CONFIG_SYS_MBAR 0xFC000000 211 212/* 213 * Low Level Configuration Settings 214 * (address mappings, register initial values, etc.) 215 * You should know what you are doing if you make changes here. 216 */ 217 218/*----------------------------------------------------------------------- 219 * Definitions for initial stack pointer and data area (in DPRAM) 220 */ 221#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 222#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 223#define CONFIG_SYS_INIT_RAM_CTRL 0x221 224#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 225#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 226#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 227 228/*----------------------------------------------------------------------- 229 * Start addresses for the final memory configuration 230 * (Set up by the startup code) 231 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 232 */ 233#define CONFIG_SYS_SDRAM_BASE 0x40000000 234#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 235#define CONFIG_SYS_SDRAM_CFG1 0x33633F30 236#define CONFIG_SYS_SDRAM_CFG2 0x57670000 237#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 238#define CONFIG_SYS_SDRAM_EMOD 0x80810000 239#define CONFIG_SYS_SDRAM_MODE 0x008D0000 240#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 241 242#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 243#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 244 245#ifdef CONFIG_CF_SBF 246# define CONFIG_SERIAL_BOOT 247# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 248#else 249# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 250#endif 251#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 252#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 253 254/* Reserve 256 kB for malloc() */ 255#define CONFIG_SYS_MALLOC_LEN (256 << 10) 256/* 257 * For booting Linux, the board info and command line data 258 * have to be in the first 8 MB of memory, since this is 259 * the maximum mapped by the Linux kernel during initialization ?? 260 */ 261/* Initial Memory map for Linux */ 262#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 263 264/* Configuration for environment 265 * Environment is not embedded in u-boot. First time runing may have env 266 * crc error warning if there is no correct environment on the flash. 267 */ 268#if defined(CONFIG_SYS_STMICRO_BOOT) 269# define CONFIG_ENV_IS_IN_SPI_FLASH 1 270# define CONFIG_ENV_SPI_CS 1 271# define CONFIG_ENV_OFFSET 0x20000 272# define CONFIG_ENV_SIZE 0x2000 273# define CONFIG_ENV_SECT_SIZE 0x10000 274#else 275# define CONFIG_ENV_IS_IN_FLASH 1 276# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 277# define CONFIG_ENV_SIZE 0x2000 278# define CONFIG_ENV_SECT_SIZE 0x20000 279#endif 280#undef CONFIG_ENV_OVERWRITE 281 282/* FLASH organization */ 283#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 284 285#define CONFIG_SYS_FLASH_CFI 286#ifdef CONFIG_SYS_FLASH_CFI 287 288# define CONFIG_FLASH_CFI_DRIVER 1 289# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 290# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 291# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 292# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 293# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 294# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 295# define CONFIG_SYS_FLASH_CHECKSUM 296# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 297 298#endif 299 300/* 301 * This is setting for JFFS2 support in u-boot. 302 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 303 */ 304#ifdef CONFIG_CMD_JFFS2 305# define CONFIG_JFFS2_DEV "nor0" 306# define CONFIG_JFFS2_PART_SIZE 0x01000000 307# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 308#endif 309 310/* Cache Configuration */ 311#define CONFIG_SYS_CACHELINE_SIZE 16 312 313#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 314 CONFIG_SYS_INIT_RAM_SIZE - 8) 315#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 316 CONFIG_SYS_INIT_RAM_SIZE - 4) 317#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 318#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 319#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 320 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 321 CF_ACR_EN | CF_ACR_SM_ALL) 322#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 323 CF_CACR_ICINVA | CF_CACR_EUSP) 324#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 325 CF_CACR_DEC | CF_CACR_DDCM_P | \ 326 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 327 328/*----------------------------------------------------------------------- 329 * Memory bank definitions 330 */ 331/* 332 * CS0 - NOR Flash 16MB 333 * CS1 - Available 334 * CS2 - Available 335 * CS3 - Available 336 * CS4 - Available 337 * CS5 - Available 338 */ 339 340 /* Flash */ 341#define CONFIG_SYS_CS0_BASE 0x00000000 342#define CONFIG_SYS_CS0_MASK 0x00FF0001 343#define CONFIG_SYS_CS0_CTRL 0x00004D80 344 345#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE 346 347#endif /* _M54451EVB_H */ 348