1/* 2 * (C) Copyright 2000 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * Configuation settings for the MBX8xx board. 7 * 8 * ----------------------------------------------------------------- 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27/* 28 * Changed 2002-10-01 29 * Added PCMCIA defines mostly taken from other U-Boot boards that 30 * have PCMCIA already working. If you find any bugs, incorrect assumptions 31 * feel free to fix them yourself and submit a patch. 32 * Rod Boyce <rod_boyce@stratexnet.com. 33 */ 34/* 35 * board/config.h - configuration options, board specific 36 */ 37 38#ifndef __CONFIG_H 39#define __CONFIG_H 40 41/* 42 * High Level Configuration Options 43 * (easy to change) 44 */ 45 46#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 47#define CONFIG_MBX 1 /* ...on an MBX module */ 48 49#define CONFIG_SYS_TEXT_BASE 0xfe000000 50 51#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 52#undef CONFIG_8xx_CONS_SMC2 53#undef CONFIG_8xx_CONS_NONE 54#define CONFIG_BAUDRATE 9600 55/* Define this to use the PCI bus */ 56#undef CONFIG_USE_PCI 57 58#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 59#define CONFIG_8xx_GCLK_FREQ (50000000UL) 60#if 1 61#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 62#else 63#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 64#endif 65#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */ 66 67#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ 68 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ 69 "nfsaddrs=10.0.0.99:10.0.0.2" 70 71#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 72#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 73 74#undef CONFIG_WATCHDOG /* watchdog disabled */ 75 76 77/* 78 * BOOTP options 79 */ 80#define CONFIG_BOOTP_BOOTFILESIZE 81#define CONFIG_BOOTP_BOOTPATH 82#define CONFIG_BOOTP_GATEWAY 83#define CONFIG_BOOTP_HOSTNAME 84 85 86/* 87 * Command line configuration. 88 */ 89#define CONFIG_CMD_NET 90#define CONFIG_CMD_DFL 91#define CONFIG_CMD_SDRAM 92#define CONFIG_CMD_PCMCIA 93#define CONFIG_CMD_IDE 94 95 96#define CONFIG_DOS_PARTITION 97 98/* 99 * Miscellaneous configurable options 100 */ 101#define CONFIG_SYS_LONGHELP /* undef to save memory */ 102#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 103#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */ 104#ifdef CONFIG_SYS_HUSH_PARSER 105#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 106#endif 107#if defined(CONFIG_CMD_KGDB) 108#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 109#else 110#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111#endif 112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 116#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 117#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 118 119#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 120 121#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 122 123#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 124 125/* 126 * Low Level Configuration Settings 127 * (address mappings, register initial values, etc.) 128 * You should know what you are doing if you make changes here. 129 */ 130 131/*----------------------------------------------------------------------- 132 * Physical memory map as defined by the MBX PGM 133 */ 134#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/ 135#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */ 136#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ 137#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */ 138#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ 139#define CONFIG_SYS_PCIMEM_OR 0xA0000108 140#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ 141#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108 142 143/*----------------------------------------------------------------------- 144 * Definitions for initial stack pointer and data area (in DPRAM) 145 */ 146#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 147#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */ 148#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 149#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ 150#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE) 151#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8) 152 153/*----------------------------------------------------------------------- 154 * Offset in DPMEM where we keep the VPD data 155 */ 156#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000) 157 158/*----------------------------------------------------------------------- 159 * Start addresses for the final memory configuration 160 * (Set up by the startup code) 161 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 162 */ 163#define CONFIG_SYS_SDRAM_BASE 0x00000000 164#define CONFIG_SYS_FLASH_BASE 0xfe000000 165#ifdef DEBUG 166#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 167#else 168#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 169#endif 170#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */ 171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 172#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 173 174/* 175 * For booting Linux, the board info and command line data 176 * have to be in the first 8 MB of memory, since this is 177 * the maximum mapped by the Linux kernel during initialization. 178 */ 179#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 180 181/*----------------------------------------------------------------------- 182 * FLASH organization 183 */ 184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 185#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ 186 187#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 188#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 189 190/*----------------------------------------------------------------------- 191 * NVRAM Configuration 192 * 193 * Note: the MBX is special because there is already a firmware on this 194 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we 195 * access the NVRAM at the offset 0x1000. 196 */ 197#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ 198#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000) 199#define CONFIG_ENV_SIZE 0x1000 200 201/*----------------------------------------------------------------------- 202 * Cache Configuration 203 */ 204#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 205#if defined(CONFIG_CMD_KGDB) 206#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 207#endif 208 209/*----------------------------------------------------------------------- 210 * SYPCR - System Protection Control 11-9 211 * SYPCR can only be written once after reset! 212 *----------------------------------------------------------------------- 213 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 214 */ 215#if defined(CONFIG_WATCHDOG) 216#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 217 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 218#else 219#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) 220#endif 221 222/*----------------------------------------------------------------------- 223 * SIUMCR - SIU Module Configuration 11-6 224 *----------------------------------------------------------------------- 225 * PCMCIA config., multi-function pin tri-state 226 */ 227/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */ 228#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC ) 229 230/*----------------------------------------------------------------------- 231 * TBSCR - Time Base Status and Control 11-26 232 *----------------------------------------------------------------------- 233 * Clear Reference Interrupt Status, Timebase freezing enabled 234 */ 235#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 236 237/*----------------------------------------------------------------------- 238 * PISCR - Periodic Interrupt Status and Control 11-31 239 *----------------------------------------------------------------------- 240 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 241 */ 242#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) 243 244/*----------------------------------------------------------------------- 245 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 246 *----------------------------------------------------------------------- 247 * Reset PLL lock status sticky bit, timer expired status bit and timer 248 * interrupt status bit - leave PLL multiplication factor unchanged ! 249 */ 250#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 251 252/*----------------------------------------------------------------------- 253 * SCCR - System Clock and reset Control Register 15-27 254 *----------------------------------------------------------------------- 255 * Set clock output, timebase and RTC source and divider, 256 * power management and some other internal clocks 257 */ 258#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) 259#define CONFIG_SYS_SCCR SCCR_TBS 260 261/*----------------------------------------------------------------------- 262 * PCMCIA stuff 263 *----------------------------------------------------------------------- 264 * 265 */ 266#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 267#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 268#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 269#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 270#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 271#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 272#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 273#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 274 275#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6 276 277#define CONFIG_PCMCIA_SLOT_A 1 278 279 280/*----------------------------------------------------------------------- 281 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 282 *----------------------------------------------------------------------- 283 */ 284 285#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 286 287#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 288#undef CONFIG_IDE_LED /* LED for ide not supported */ 289#undef CONFIG_IDE_RESET /* reset for ide not supported */ 290 291#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 292#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 293 294#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 295 296#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 297 298/* Offset for data I/O */ 299#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 300 301/* Offset for normal register accesses */ 302#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 303 304/* Offset for alternate registers */ 305#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 306 307/*----------------------------------------------------------------------- 308 * Debug Entry Mode 309 *----------------------------------------------------------------------- 310 * 311 */ 312#define CONFIG_SYS_DER 0 313 314#endif /* __CONFIG_H */ 315