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24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28
29
30
31#define CONFIG_E300 1
32#define CONFIG_MPC83xx 1
33#define CONFIG_MPC8308 1
34#define CONFIG_MPC8308RDB 1
35
36#define CONFIG_SYS_TEXT_BASE 0xFE000000
37
38#define CONFIG_MISC_INIT_R
39
40
41
42
43
44
45
46#define CONFIG_TSEC1
47#define CONFIG_VSC7385_ENET
48
49
50
51
52#define CONFIG_83XX_CLKIN 33333333
53#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
54
55
56
57
58
59
60
61#define CONFIG_SYS_HRCW_LOW (\
62 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
63 HRCWL_DDR_TO_SCB_CLK_2X1 |\
64 HRCWL_SVCOD_DIV_2 |\
65 HRCWL_CSB_TO_CLKIN_4X1 |\
66 HRCWL_CORE_TO_CSB_3X1)
67
68
69
70
71
72
73
74#define CONFIG_SYS_HRCW_HIGH (\
75 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_RGMII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN)
86
87
88
89
90#define CONFIG_SYS_SICRH (\
91 SICRH_ESDHC_A_SD |\
92 SICRH_ESDHC_B_SD |\
93 SICRH_ESDHC_C_SD |\
94 SICRH_GPIO_A_TSEC2 |\
95 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
96 SICRH_IEEE1588_A_GPIO |\
97 SICRH_USB |\
98 SICRH_GTM_GPIO |\
99 SICRH_IEEE1588_B_GPIO |\
100 SICRH_ETSEC2_CRS |\
101 SICRH_GPIOSEL_1 |\
102 SICRH_TMROBI_V3P3 |\
103 SICRH_TSOBI1_V2P5 |\
104 SICRH_TSOBI2_V2P5)
105#define CONFIG_SYS_SICRL (\
106 SICRL_SPI_PF0 |\
107 SICRL_UART_PF0 |\
108 SICRL_IRQ_PF0 |\
109 SICRL_I2C2_PF0 |\
110 SICRL_ETSEC1_GTX_CLK125)
111
112
113
114
115#define CONFIG_SYS_IMMR 0xE0000000
116
117
118
119
120#define CONFIG_FSL_SERDES
121#define CONFIG_FSL_SERDES1 0xe3000
122
123
124
125
126#define CONFIG_SYS_ACR_PIPE_DEP 3
127#define CONFIG_SYS_ACR_RPTCNT 3
128#define CONFIG_SYS_SPCR_TSECEP 3
129
130
131
132
133#define CONFIG_SYS_DDR_BASE 0x00000000
134#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
135#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
136#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
137#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
138 | DDRCDR_PZ_LOZ \
139 | DDRCDR_NZ_LOZ \
140 | DDRCDR_ODT \
141 | DDRCDR_Q_DRN)
142
143
144
145
146
147
148#define CONFIG_SYS_DDR_SIZE 128
149
150#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
151#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
152 | CSCONFIG_ODT_RD_NEVER \
153 | CSCONFIG_ODT_WR_ONLY_CURRENT \
154 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
155
156#define CONFIG_SYS_DDR_TIMING_3 0x00000000
157#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
158 | (0 << TIMING_CFG0_WRT_SHIFT) \
159 | (0 << TIMING_CFG0_RRT_SHIFT) \
160 | (0 << TIMING_CFG0_WWT_SHIFT) \
161 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
162 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
163 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
164 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
165
166#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
167 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
168 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
169 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
170 | (6 << TIMING_CFG1_REFREC_SHIFT) \
171 | (2 << TIMING_CFG1_WRREC_SHIFT) \
172 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
173 | (2 << TIMING_CFG1_WRTORD_SHIFT))
174
175#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
176 | (4 << TIMING_CFG2_CPO_SHIFT) \
177 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
178 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
179 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
180 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
181 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
182
183#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
184 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
185
186#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
187 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
188 | SDRAM_CFG_DBW_32)
189
190
191#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
192#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
193 | (0x0232 << SDRAM_MODE_SD_SHIFT))
194
195#define CONFIG_SYS_DDR_MODE2 0x00000000
196
197
198
199
200#define CONFIG_SYS_MEMTEST_START 0x00001000
201#define CONFIG_SYS_MEMTEST_END 0x07f00000
202
203
204
205
206#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
207
208#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
209#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
210
211
212
213
214#define CONFIG_SYS_INIT_RAM_LOCK 1
215#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
216#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
217#define CONFIG_SYS_GBL_DATA_OFFSET \
218 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219
220
221
222
223#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
224#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
225#define CONFIG_SYS_LBC_LBCR 0x00040000
226
227
228
229
230#define CONFIG_SYS_FLASH_CFI
231#define CONFIG_FLASH_CFI_DRIVER
232#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
233
234#define CONFIG_SYS_FLASH_BASE 0xFE000000
235#define CONFIG_SYS_FLASH_SIZE 8
236#define CONFIG_SYS_FLASH_PROTECTION 1
237
238
239#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
240#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
241
242#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
243 | BR_PS_16 \
244 | BR_MS_GPCM \
245 | BR_V)
246#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
247 | OR_UPM_XAM \
248 | OR_GPCM_CSNT \
249 | OR_GPCM_ACS_DIV2 \
250 | OR_GPCM_XACS \
251 | OR_GPCM_SCY_15 \
252 | OR_GPCM_TRLX_SET \
253 | OR_GPCM_EHTR_SET)
254
255#define CONFIG_SYS_MAX_FLASH_BANKS 1
256
257#define CONFIG_SYS_MAX_FLASH_SECT 135
258
259#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
260#define CONFIG_SYS_FLASH_WRITE_TOUT 500
261
262
263
264
265#define CONFIG_SYS_NAND_BASE 0xE0600000
266#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
267#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
268 | BR_DECC_CHK_GEN \
269 | BR_PS_8 \
270 | BR_MS_FCM \
271 | BR_V)
272#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
273 | OR_FCM_CSCT \
274 | OR_FCM_CST \
275 | OR_FCM_CHT \
276 | OR_FCM_SCY_1 \
277 | OR_FCM_TRLX \
278 | OR_FCM_EHTR)
279
280
281#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
282#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
283
284#ifdef CONFIG_VSC7385_ENET
285#define CONFIG_TSEC2
286
287#define CONFIG_SYS_VSC7385_BASE 0xF0000000
288#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
289#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
290 | BR_PS_8 \
291 | BR_MS_GPCM \
292 | BR_V)
293
294#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
295 | OR_GPCM_CSNT \
296 | OR_GPCM_XACS \
297 | OR_GPCM_SCY_15 \
298 | OR_GPCM_SETA \
299 | OR_GPCM_TRLX_SET \
300 | OR_GPCM_EHTR_SET)
301
302
303#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
304
305#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
306
307#define CONFIG_VSC7385_IMAGE 0xFE7FE000
308#define CONFIG_VSC7385_IMAGE_SIZE 8192
309#endif
310
311
312
313#define CONFIG_CONS_INDEX 1
314#define CONFIG_SYS_NS16550
315#define CONFIG_SYS_NS16550_SERIAL
316#define CONFIG_SYS_NS16550_REG_SIZE 1
317#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
318
319#define CONFIG_SYS_BAUDRATE_TABLE \
320 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
321
322#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
323#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
324
325
326#define CONFIG_SYS_HUSH_PARSER
327#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
328
329
330#define CONFIG_OF_LIBFDT 1
331#define CONFIG_OF_BOARD_SETUP 1
332#define CONFIG_OF_STDOUT_VIA_ALIAS 1
333
334
335#define CONFIG_HARD_I2C
336#define CONFIG_FSL_I2C
337#define CONFIG_I2C_MULTI_BUS
338#define CONFIG_SYS_I2C_SPEED 400000
339#define CONFIG_SYS_I2C_SLAVE 0x7F
340#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
341#define CONFIG_SYS_I2C_OFFSET 0x3000
342#define CONFIG_SYS_I2C2_OFFSET 0x3100
343
344
345
346
347
348#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
349
350
351
352
353#define CONFIG_RTC_DS1337
354#define CONFIG_SYS_I2C_RTC_ADDR 0x68
355
356
357
358
359
360#define CONFIG_SYS_PCIE1_BASE 0xA0000000
361#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
362#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
363#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
364#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
365#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
366#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
367#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
368#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
369
370
371#define CONFIG_SYS_SCCR_PCIEXP1CM 1
372
373#define CONFIG_PCI
374#define CONFIG_PCIE
375
376#define CONFIG_PCI_PNP
377
378#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
379#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
380
381
382
383
384#define CONFIG_TSEC_ENET
385#define CONFIG_SYS_TSEC1_OFFSET 0x24000
386#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
387#define CONFIG_SYS_TSEC2_OFFSET 0x25000
388#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
389
390
391
392
393#define CONFIG_MII 1
394#define CONFIG_TSEC1_NAME "eTSEC0"
395#define CONFIG_TSEC2_NAME "eTSEC1"
396#define TSEC1_PHY_ADDR 2
397#define TSEC2_PHY_ADDR 1
398#define TSEC1_PHYIDX 0
399#define TSEC2_PHYIDX 0
400#define TSEC1_FLAGS TSEC_GIGABIT
401#define TSEC2_FLAGS TSEC_GIGABIT
402
403
404#define CONFIG_ETHPRIME "eTSEC0"
405
406
407
408
409#define CONFIG_ENV_IS_IN_FLASH 1
410#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
411 CONFIG_SYS_MONITOR_LEN)
412#define CONFIG_ENV_SECT_SIZE 0x10000
413#define CONFIG_ENV_SIZE 0x2000
414#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
415#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
416
417#define CONFIG_LOADS_ECHO 1
418#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
419
420
421
422
423#define CONFIG_BOOTP_BOOTFILESIZE
424#define CONFIG_BOOTP_BOOTPATH
425#define CONFIG_BOOTP_GATEWAY
426#define CONFIG_BOOTP_HOSTNAME
427
428
429
430
431#include <config_cmd_default.h>
432
433#define CONFIG_CMD_DATE
434#define CONFIG_CMD_DHCP
435#define CONFIG_CMD_I2C
436#define CONFIG_CMD_MII
437#define CONFIG_CMD_NET
438#define CONFIG_CMD_PCI
439#define CONFIG_CMD_PING
440
441#define CONFIG_CMDLINE_EDITING 1
442
443
444
445
446#define CONFIG_SYS_LONGHELP
447#define CONFIG_SYS_LOAD_ADDR 0x2000000
448#define CONFIG_SYS_PROMPT "=> "
449
450#define CONFIG_SYS_CBSIZE 1024
451
452
453#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
454#define CONFIG_SYS_MAXARGS 16
455
456#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
457#define CONFIG_SYS_HZ 1000
458
459
460
461
462
463
464#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
465
466
467
468
469#define CONFIG_SYS_HID0_INIT 0x000000000
470#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
471 HID0_ENABLE_INSTRUCTION_CACHE | \
472 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
473#define CONFIG_SYS_HID2 HID2_HBE
474
475
476
477
478
479
480#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
481 BATL_MEMCOHERENCE)
482#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
483 BATU_VS | BATU_VP)
484#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
485#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
486
487
488#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
489 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
490#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
491 BATU_VP)
492#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
493#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
494
495
496#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
497 BATL_MEMCOHERENCE)
498#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
499 BATU_VS | BATU_VP)
500#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
501 BATL_CACHEINHIBIT | \
502 BATL_GUARDEDSTORAGE)
503#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
504
505
506#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
507#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
508 BATU_VS | BATU_VP)
509#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
510#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
511
512
513
514
515
516#define CONFIG_ENV_OVERWRITE
517
518#if defined(CONFIG_TSEC_ENET)
519#define CONFIG_HAS_ETH0
520#define CONFIG_HAS_ETH1
521#endif
522
523#define CONFIG_BAUDRATE 115200
524
525#define CONFIG_LOADADDR 800000
526
527#define CONFIG_BOOTDELAY 5
528
529#define xstr(s) str(s)
530#define str(s) #s
531
532#define CONFIG_EXTRA_ENV_SETTINGS \
533 "netdev=eth0\0" \
534 "consoledev=ttyS0\0" \
535 "nfsargs=setenv bootargs root=/dev/nfs rw " \
536 "nfsroot=${serverip}:${rootpath}\0" \
537 "ramargs=setenv bootargs root=/dev/ram rw\0" \
538 "addip=setenv bootargs ${bootargs} " \
539 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
540 ":${hostname}:${netdev}:off panic=1\0" \
541 "addtty=setenv bootargs ${bootargs}" \
542 " console=${consoledev},${baudrate}\0" \
543 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
544 "addmisc=setenv bootargs ${bootargs}\0" \
545 "kernel_addr=FE080000\0" \
546 "fdt_addr=FE280000\0" \
547 "ramdisk_addr=FE290000\0" \
548 "u-boot=mpc8308rdb/u-boot.bin\0" \
549 "kernel_addr_r=1000000\0" \
550 "fdt_addr_r=C00000\0" \
551 "hostname=mpc8308rdb\0" \
552 "bootfile=mpc8308rdb/uImage\0" \
553 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
554 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
555 "flash_self=run ramargs addip addtty addmtd addmisc;" \
556 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
557 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
558 "bootm ${kernel_addr} - ${fdt_addr}\0" \
559 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
560 "tftp ${fdt_addr_r} ${fdtfile};" \
561 "run nfsargs addip addtty addmtd addmisc;" \
562 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
563 "bootcmd=run flash_self\0" \
564 "load=tftp ${loadaddr} ${u-boot}\0" \
565 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
566 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
567 " +${filesize};cp.b ${fileaddr} " \
568 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
569 "upd=run load update\0" \
570
571#endif
572