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25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29
30
31
32#define CONFIG_E300 1
33#define CONFIG_MPC83xx 1
34#define CONFIG_MPC831x 1
35#define CONFIG_MPC8313 1
36#define CONFIG_MPC8313ERDB 1
37
38#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
39#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
40#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
41#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
42#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
43#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
44
45#ifdef CONFIG_NAND_U_BOOT
46#define CONFIG_SYS_TEXT_BASE 0x00100000
47#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
48#ifdef CONFIG_NAND_SPL
49#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
50#endif
51#endif
52
53#ifndef CONFIG_SYS_TEXT_BASE
54#define CONFIG_SYS_TEXT_BASE 0xFE000000
55#endif
56
57#ifndef CONFIG_SYS_MONITOR_BASE
58#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
59#endif
60
61#define CONFIG_PCI
62#define CONFIG_FSL_ELBC 1
63
64#define CONFIG_MISC_INIT_R
65
66
67
68
69
70
71
72#define CONFIG_VSC7385_ENET
73#define CONFIG_TSEC2
74
75#ifdef CONFIG_SYS_66MHZ
76#define CONFIG_83XX_CLKIN 66666667
77#elif defined(CONFIG_SYS_33MHZ)
78#define CONFIG_83XX_CLKIN 33333333
79#else
80#error Unknown oscillator frequency.
81#endif
82
83#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
84
85#define CONFIG_BOARD_EARLY_INIT_F
86
87#define CONFIG_SYS_IMMR 0xE0000000
88
89#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
90#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
91#endif
92
93#define CONFIG_SYS_MEMTEST_START 0x00001000
94#define CONFIG_SYS_MEMTEST_END 0x07f00000
95
96
97
98
99
100#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
101
102#define CONFIG_SYS_ACR_PIPE_DEP 3
103#define CONFIG_SYS_ACR_RPTCNT 3
104
105
106
107
108
109
110
111#ifdef CONFIG_VSC7385_ENET
112
113#define CONFIG_TSEC1
114
115
116#define CONFIG_VSC7385_IMAGE 0xFE7FE000
117#define CONFIG_VSC7385_IMAGE_SIZE 8192
118
119#endif
120
121
122
123
124#define CONFIG_SYS_DDR_BASE 0x00000000
125#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
126#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
127
128
129
130
131
132#define CONFIG_SYS_DDR_SIZE 128
133#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
134 | CSCONFIG_ODT_RD_NEVER \
135 | CSCONFIG_ODT_WR_ONLY_CURRENT \
136 | CSCONFIG_ROW_BIT_13 \
137 | CSCONFIG_COL_BIT_10)
138
139
140#define CONFIG_SYS_DDR_TIMING_3 0x00000000
141#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
142 | (0 << TIMING_CFG0_WRT_SHIFT) \
143 | (0 << TIMING_CFG0_RRT_SHIFT) \
144 | (0 << TIMING_CFG0_WWT_SHIFT) \
145 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
146 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
147 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
148 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
149
150#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
151 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
152 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
153 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
154 | (10 << TIMING_CFG1_REFREC_SHIFT) \
155 | (3 << TIMING_CFG1_WRREC_SHIFT) \
156 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
157 | (2 << TIMING_CFG1_WRTORD_SHIFT))
158
159#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
160 | (5 << TIMING_CFG2_CPO_SHIFT) \
161 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
162 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
163 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
164 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
165 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
166
167#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
168 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
169
170#if defined(CONFIG_DDR_2T_TIMING)
171#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
172 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
173 | SDRAM_CFG_DBW_32 \
174 | SDRAM_CFG_2T_EN)
175
176#else
177#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
178 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
179 | SDRAM_CFG_DBW_32)
180
181#endif
182#define CONFIG_SYS_SDRAM_CFG2 0x00401000
183
184#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
185 | (0x0632 << SDRAM_MODE_SD_SHIFT))
186
187#define CONFIG_SYS_DDR_MODE_2 0x8000C000
188
189#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
190
191#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
192 | DDRCDR_PZ_NOMZ \
193 | DDRCDR_NZ_NOMZ \
194 | DDRCDR_M_ODR)
195
196
197
198
199#define CONFIG_SYS_FLASH_CFI
200#define CONFIG_FLASH_CFI_DRIVER
201#define CONFIG_SYS_FLASH_BASE 0xFE000000
202#define CONFIG_SYS_FLASH_SIZE 8
203#define CONFIG_SYS_FLASH_PROTECTION 1
204#define CONFIG_SYS_FLASH_EMPTY_INFO
205#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
206
207#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
208 | BR_PS_16 \
209 | BR_MS_GPCM \
210 | BR_V)
211#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
212 | OR_GPCM_XACS \
213 | OR_GPCM_SCY_9 \
214 | OR_GPCM_EHTR \
215 | OR_GPCM_EAD)
216
217
218#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
219
220#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
221
222#define CONFIG_SYS_MAX_FLASH_BANKS 1
223#define CONFIG_SYS_MAX_FLASH_SECT 135
224
225#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
226#define CONFIG_SYS_FLASH_WRITE_TOUT 500
227
228#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
229 !defined(CONFIG_NAND_SPL)
230#define CONFIG_SYS_RAMBOOT
231#endif
232
233#define CONFIG_SYS_INIT_RAM_LOCK 1
234#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
235#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
236
237#define CONFIG_SYS_GBL_DATA_OFFSET \
238 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
239#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
240
241
242#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
243#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
244
245
246
247
248#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
249#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
250#define CONFIG_SYS_LBC_LBCR (0x00040000 \
251 | (0xFF << LBCR_BMT_SHIFT) \
252 | 0xF)
253
254
255#define CONFIG_SYS_LBC_MRTPR 0x20000000
256
257
258#ifdef CONFIG_NAND_SPL
259#define CONFIG_SYS_NAND_BASE 0xFFF00000
260#else
261#define CONFIG_SYS_NAND_BASE 0xE2800000
262#endif
263
264#define CONFIG_MTD_DEVICE
265#define CONFIG_MTD_PARTITION
266#define CONFIG_CMD_MTDPARTS
267#define MTDIDS_DEFAULT "nand0=e2800000.flash"
268#define MTDPARTS_DEFAULT \
269 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
270
271#define CONFIG_SYS_MAX_NAND_DEVICE 1
272#define CONFIG_MTD_NAND_VERIFY_WRITE
273#define CONFIG_CMD_NAND 1
274#define CONFIG_NAND_FSL_ELBC 1
275#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
276#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
277
278
279#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
280 | BR_DECC_CHK_GEN \
281 | BR_PS_8 \
282 | BR_MS_FCM \
283 | BR_V)
284#define CONFIG_SYS_NAND_OR_PRELIM \
285 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
286 | OR_FCM_CSCT \
287 | OR_FCM_CST \
288 | OR_FCM_CHT \
289 | OR_FCM_SCY_1 \
290 | OR_FCM_TRLX \
291 | OR_FCM_EHTR)
292
293
294#ifdef CONFIG_NAND_U_BOOT
295#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
296#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
297#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
298#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
299#else
300#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
301#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
302#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
303#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
304#endif
305
306#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
307#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
308
309#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
310#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
311
312
313#define CONFIG_SYS_BCSR_ADDR 0xFA000000
314#define CONFIG_SYS_BCSR_SIZE (32 * 1024)
315
316#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
317 | BR_PS_8 \
318 | BR_MS_GPCM \
319 | BR_V)
320
321#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
322 | OR_GPCM_CSNT \
323 | OR_GPCM_ACS_DIV2 \
324 | OR_GPCM_XACS \
325 | OR_GPCM_SCY_15 \
326 | OR_GPCM_TRLX_SET \
327 | OR_GPCM_EHTR_SET \
328 | OR_GPCM_EAD)
329
330#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
331#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
332
333
334
335#ifdef CONFIG_VSC7385_ENET
336
337
338#define CONFIG_SYS_VSC7385_BASE 0xF0000000
339#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
340
341#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
342 | BR_PS_8 \
343 | BR_MS_GPCM \
344 | BR_V)
345#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
346 | OR_GPCM_CSNT \
347 | OR_GPCM_XACS \
348 | OR_GPCM_SCY_15 \
349 | OR_GPCM_SETA \
350 | OR_GPCM_TRLX_SET \
351 | OR_GPCM_EHTR_SET \
352 | OR_GPCM_EAD)
353
354
355
356#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
357#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
358
359#endif
360
361
362#define CONFIG_OF_LIBFDT 1
363#define CONFIG_OF_BOARD_SETUP 1
364#define CONFIG_OF_STDOUT_VIA_ALIAS 1
365
366
367
368
369#define CONFIG_CONS_INDEX 1
370#define CONFIG_SYS_NS16550
371#define CONFIG_SYS_NS16550_SERIAL
372#define CONFIG_SYS_NS16550_REG_SIZE 1
373
374#define CONFIG_SYS_BAUDRATE_TABLE \
375 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
376
377#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
378#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
379
380
381#define CONFIG_SYS_HUSH_PARSER
382#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
383
384
385#define CONFIG_HARD_I2C
386#define CONFIG_FSL_I2C
387#define CONFIG_I2C_MULTI_BUS
388#define CONFIG_SYS_I2C_SPEED 400000
389#define CONFIG_SYS_I2C_SLAVE 0x7F
390#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
391#define CONFIG_SYS_I2C_OFFSET 0x3000
392#define CONFIG_SYS_I2C2_OFFSET 0x3100
393
394
395
396
397
398#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
399#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
400#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
401#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
402#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
403#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
404#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
405#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
406#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
407
408#define CONFIG_PCI_PNP
409#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
410
411
412
413
414#define CONFIG_TSEC_ENET
415
416#define CONFIG_GMII
417
418#ifdef CONFIG_TSEC1
419#define CONFIG_HAS_ETH0
420#define CONFIG_TSEC1_NAME "TSEC0"
421#define CONFIG_SYS_TSEC1_OFFSET 0x24000
422#define TSEC1_PHY_ADDR 0x1c
423#define TSEC1_FLAGS TSEC_GIGABIT
424#define TSEC1_PHYIDX 0
425#endif
426
427#ifdef CONFIG_TSEC2
428#define CONFIG_HAS_ETH1
429#define CONFIG_TSEC2_NAME "TSEC1"
430#define CONFIG_SYS_TSEC2_OFFSET 0x25000
431#define TSEC2_PHY_ADDR 4
432#define TSEC2_FLAGS TSEC_GIGABIT
433#define TSEC2_PHYIDX 0
434#endif
435
436
437
438#define CONFIG_ETHPRIME "TSEC1"
439
440
441
442
443#define CONFIG_RTC_DS1337
444#define CONFIG_SYS_I2C_RTC_ADDR 0x68
445
446
447
448
449#if defined(CONFIG_NAND_U_BOOT)
450 #define CONFIG_ENV_IS_IN_NAND 1
451 #define CONFIG_ENV_OFFSET (512 * 1024)
452 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
453 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
454 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
455 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
456 #define CONFIG_ENV_OFFSET_REDUND \
457 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
458#elif !defined(CONFIG_SYS_RAMBOOT)
459 #define CONFIG_ENV_IS_IN_FLASH 1
460 #define CONFIG_ENV_ADDR \
461 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
462 #define CONFIG_ENV_SECT_SIZE 0x10000
463 #define CONFIG_ENV_SIZE 0x2000
464
465
466#else
467 #define CONFIG_ENV_IS_NOWHERE 1
468 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
469 #define CONFIG_ENV_SIZE 0x2000
470#endif
471
472#define CONFIG_LOADS_ECHO 1
473#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
474
475
476
477
478#define CONFIG_BOOTP_BOOTFILESIZE
479#define CONFIG_BOOTP_BOOTPATH
480#define CONFIG_BOOTP_GATEWAY
481#define CONFIG_BOOTP_HOSTNAME
482
483
484
485
486
487#include <config_cmd_default.h>
488
489#define CONFIG_CMD_PING
490#define CONFIG_CMD_DHCP
491#define CONFIG_CMD_I2C
492#define CONFIG_CMD_MII
493#define CONFIG_CMD_DATE
494#define CONFIG_CMD_PCI
495
496#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
497 #undef CONFIG_CMD_SAVEENV
498 #undef CONFIG_CMD_LOADS
499#endif
500
501#define CONFIG_CMDLINE_EDITING 1
502#define CONFIG_AUTO_COMPLETE
503
504
505
506
507#define CONFIG_SYS_LONGHELP
508#define CONFIG_SYS_LOAD_ADDR 0x2000000
509#define CONFIG_SYS_PROMPT "=> "
510#define CONFIG_SYS_CBSIZE 1024
511
512
513#define CONFIG_SYS_PBSIZE \
514 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
515#define CONFIG_SYS_MAXARGS 16
516
517#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
518#define CONFIG_SYS_HZ 1000
519
520
521
522
523
524
525
526#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
527
528#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
529
530#ifdef CONFIG_SYS_66MHZ
531
532
533
534#define CONFIG_SYS_HRCW_LOW (\
535 0x20000000 |\
536 HRCWL_DDRCM |\
537 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
538 HRCWL_DDR_TO_SCB_CLK_2X1 |\
539 HRCWL_CSB_TO_CLKIN_2X1 |\
540 HRCWL_CORE_TO_CSB_2X1)
541
542#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
543
544#elif defined(CONFIG_SYS_33MHZ)
545
546
547
548#define CONFIG_SYS_HRCW_LOW (\
549 0x20000000 |\
550 HRCWL_DDRCM |\
551 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
552 HRCWL_DDR_TO_SCB_CLK_2X1 |\
553 HRCWL_CSB_TO_CLKIN_5X1 |\
554 HRCWL_CORE_TO_CSB_2X1)
555
556#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
557
558#endif
559
560#define CONFIG_SYS_HRCW_HIGH_BASE (\
561 HRCWH_PCI_HOST |\
562 HRCWH_PCI1_ARBITER_ENABLE |\
563 HRCWH_CORE_ENABLE |\
564 HRCWH_BOOTSEQ_DISABLE |\
565 HRCWH_SW_WATCHDOG_DISABLE |\
566 HRCWH_TSEC1M_IN_RGMII |\
567 HRCWH_TSEC2M_IN_RGMII |\
568 HRCWH_BIG_ENDIAN)
569
570#ifdef CONFIG_NAND_SPL
571#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
572 HRCWH_FROM_0XFFF00100 |\
573 HRCWH_ROM_LOC_NAND_SP_8BIT |\
574 HRCWH_RL_EXT_NAND)
575#else
576#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
577 HRCWH_FROM_0X00000100 |\
578 HRCWH_ROM_LOC_LOCAL_16BIT |\
579 HRCWH_RL_EXT_LEGACY)
580#endif
581
582
583#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2)
584#define CONFIG_SYS_SICRL SICRL_USBDR_10
585
586#define CONFIG_SYS_HID0_INIT 0x000000000
587#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
588 HID0_ENABLE_INSTRUCTION_CACHE | \
589 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
590
591#define CONFIG_SYS_HID2 HID2_HBE
592
593#define CONFIG_HIGH_BATS 1
594
595
596#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
597#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
598 | BATU_BL_256M \
599 | BATU_VS \
600 | BATU_VP)
601
602
603#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
604#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
605 | BATU_BL_256M \
606 | BATU_VS \
607 | BATU_VP)
608#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
609 | BATL_PP_RW \
610 | BATL_CACHEINHIBIT \
611 | BATL_GUARDEDSTORAGE)
612#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
613 | BATU_BL_256M \
614 | BATU_VS \
615 | BATU_VP)
616
617
618#define CONFIG_SYS_IBAT3L (0)
619#define CONFIG_SYS_IBAT3U (0)
620#define CONFIG_SYS_IBAT4L (0)
621#define CONFIG_SYS_IBAT4U (0)
622
623
624#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
625 | BATL_PP_RW \
626 | BATL_CACHEINHIBIT \
627 | BATL_GUARDEDSTORAGE)
628#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
629 | BATU_BL_256M \
630 | BATU_VS \
631 | BATU_VP)
632
633
634#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
635#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
636
637#define CONFIG_SYS_IBAT7L (0)
638#define CONFIG_SYS_IBAT7U (0)
639
640#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
641#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
642#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
643#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
644#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
645#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
646#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
647#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
648#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
649#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
650#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
651#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
652#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
653#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
654#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
655#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
656
657
658
659
660#define CONFIG_ENV_OVERWRITE
661
662#define CONFIG_NETDEV "eth1"
663
664#define CONFIG_HOSTNAME mpc8313erdb
665#define CONFIG_ROOTPATH "/nfs/root/path"
666#define CONFIG_BOOTFILE "uImage"
667
668#define CONFIG_UBOOTPATH "u-boot.bin"
669#define CONFIG_FDTFILE "mpc8313erdb.dtb"
670
671
672#define CONFIG_LOADADDR 800000
673#define CONFIG_BOOTDELAY 6
674#define CONFIG_BAUDRATE 115200
675
676#define XMK_STR(x) #x
677#define MK_STR(x) XMK_STR(x)
678
679#define CONFIG_EXTRA_ENV_SETTINGS \
680 "netdev=" CONFIG_NETDEV "\0" \
681 "ethprime=TSEC1\0" \
682 "uboot=" CONFIG_UBOOTPATH "\0" \
683 "tftpflash=tftpboot $loadaddr $uboot; " \
684 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
685 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
686 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
687 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
688 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
689 "fdtaddr=780000\0" \
690 "fdtfile=" CONFIG_FDTFILE "\0" \
691 "console=ttyS0\0" \
692 "setbootargs=setenv bootargs " \
693 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
694 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
695 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
696 "$netdev:off " \
697 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
698
699#define CONFIG_NFSBOOTCOMMAND \
700 "setenv rootdev /dev/nfs;" \
701 "run setbootargs;" \
702 "run setipargs;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr - $fdtaddr"
706
707#define CONFIG_RAMBOOTCOMMAND \
708 "setenv rootdev /dev/ram;" \
709 "run setbootargs;" \
710 "tftp $ramdiskaddr $ramdiskfile;" \
711 "tftp $loadaddr $bootfile;" \
712 "tftp $fdtaddr $fdtfile;" \
713 "bootm $loadaddr $ramdiskaddr $fdtaddr"
714
715#undef MK_STR
716#undef XMK_STR
717
718#endif
719