1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 39#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ 40 41#define CONFIG_SYS_TEXT_BASE 0x40000000 42 43#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 44#define CONFIG_SYS_SMC_RXBUFLEN 128 45#define CONFIG_SYS_MAXIDLE 10 46#define CONFIG_BAUDRATE 115200 47#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 48 49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 50 51#define CONFIG_BOARD_TYPES 1 /* support board types */ 52 53#undef CONFIG_BOOTARGS 54#define CONFIG_BOOTCOMMAND \ 55 "bootp; " \ 56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 58 "bootm" 59 60#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 61#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 62 63#undef CONFIG_WATCHDOG /* watchdog disabled */ 64 65#undef CONFIG_STATUS_LED /* Status LED not enabled */ 66 67#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 68 69/* 70 * BOOTP options 71 */ 72#define CONFIG_BOOTP_SUBNETMASK 73#define CONFIG_BOOTP_GATEWAY 74#define CONFIG_BOOTP_HOSTNAME 75#define CONFIG_BOOTP_BOOTPATH 76#define CONFIG_BOOTP_BOOTFILESIZE 77 78 79#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 80 81 82/* 83 * Command line configuration. 84 */ 85#include <config_cmd_default.h> 86 87#define CONFIG_CMD_DHCP 88#define CONFIG_CMD_DATE 89 90 91/* 92 * Miscellaneous configurable options 93 */ 94#define CONFIG_SYS_LONGHELP /* undef to save memory */ 95#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 96#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG) 97#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 98#else 99#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 100#endif 101#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 102#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 104 105#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 106#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 107 108#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 109 110#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 111 112#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 113 114/* 115 * Low Level Configuration Settings 116 * (address mappings, register initial values, etc.) 117 * You should know what you are doing if you make changes here. 118 */ 119/*----------------------------------------------------------------------- 120 * Internal Memory Mapped Register 121 */ 122#define CONFIG_SYS_IMMR 0xFFF00000 123 124/*----------------------------------------------------------------------- 125 * Definitions for initial stack pointer and data area (in DPRAM) 126 */ 127#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 128#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 129#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 130#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 131 132/*----------------------------------------------------------------------- 133 * Start addresses for the final memory configuration 134 * (Set up by the startup code) 135 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 136 */ 137#define CONFIG_SYS_SDRAM_BASE 0x00000000 138#define CONFIG_SYS_FLASH_BASE 0x40000000 139#if defined(DEBUG) 140#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 141#else 142#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 143#endif 144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 145#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 146 147/* 148 * For booting Linux, the board info and command line data 149 * have to be in the first 8 MB of memory, since this is 150 * the maximum mapped by the Linux kernel during initialization. 151 */ 152#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 153 154/*----------------------------------------------------------------------- 155 * FLASH organization 156 */ 157/* use CFI flash driver */ 158#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 159#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 160#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 161#define CONFIG_SYS_FLASH_EMPTY_INFO 162#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 163#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 164#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 165 166#define CONFIG_ENV_IS_IN_FLASH 1 167#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 168#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 169 170#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 171 172/*----------------------------------------------------------------------- 173 * Hardware Information Block 174 */ 175#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 176#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 177#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 178 179/*----------------------------------------------------------------------- 180 * Cache Configuration 181 */ 182#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 183#if defined(CONFIG_CMD_KGDB) 184#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 185#endif 186 187/*----------------------------------------------------------------------- 188 * SYPCR - System Protection Control 11-9 189 * SYPCR can only be written once after reset! 190 *----------------------------------------------------------------------- 191 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 192 */ 193#if defined(CONFIG_WATCHDOG) 194#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 195 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 196#else 197#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 198#endif 199 200/*----------------------------------------------------------------------- 201 * SIUMCR - SIU Module Configuration 11-6 202 *----------------------------------------------------------------------- 203 * PCMCIA config., multi-function pin tri-state 204 */ 205#ifndef CONFIG_CAN_DRIVER 206#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 207#else /* we must activate GPL5 in the SIUMCR for CAN */ 208#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 209#endif /* CONFIG_CAN_DRIVER */ 210 211/*----------------------------------------------------------------------- 212 * TBSCR - Time Base Status and Control 11-26 213 *----------------------------------------------------------------------- 214 * Clear Reference Interrupt Status, Timebase freezing enabled 215 */ 216#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 217 218/*----------------------------------------------------------------------- 219 * RTCSC - Real-Time Clock Status and Control Register 11-27 220 *----------------------------------------------------------------------- 221 */ 222#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 223 224/*----------------------------------------------------------------------- 225 * PISCR - Periodic Interrupt Status and Control 11-31 226 *----------------------------------------------------------------------- 227 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 228 */ 229#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 230 231/*----------------------------------------------------------------------- 232 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 233 *----------------------------------------------------------------------- 234 * Reset PLL lock status sticky bit, timer expired status bit and timer 235 * interrupt status bit 236 * 237 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! 238 */ 239#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ 240#define CONFIG_SYS_PLPRCR \ 241 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) 242#else 243#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 244#endif /* TQM8xxL_80MHz */ 245 246/*----------------------------------------------------------------------- 247 * SCCR - System Clock and reset Control Register 15-27 248 *----------------------------------------------------------------------- 249 * Set clock output, timebase and RTC source and divider, 250 * power management and some other internal clocks 251 */ 252#define SCCR_MASK SCCR_EBDF11 253#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ 254#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ 255 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 256 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 257 SCCR_DFALCD00) 258#else /* up to 50 MHz we use a 1:1 clock */ 259#define CONFIG_SYS_SCCR (SCCR_TBS | \ 260 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 261 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 262 SCCR_DFALCD00) 263#endif /* TQM8xxL_80MHz */ 264 265/*----------------------------------------------------------------------- 266 * PCMCIA stuff 267 *----------------------------------------------------------------------- 268 * 269 */ 270#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 271#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 272#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 273#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 274#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 275#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 276#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 277#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 278 279/*----------------------------------------------------------------------- 280 * 281 *----------------------------------------------------------------------- 282 * 283 */ 284#define CONFIG_SYS_DER 0 285 286/* 287 * Init Memory Controller: 288 * 289 * BR0/1 and OR0/1 (FLASH) 290 */ 291 292#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 293#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 294 295/* used to re-map FLASH both when starting from SRAM or FLASH: 296 * restrict access enough to keep SRAM working (if any) 297 * but not too much to meddle with FLASH accesses 298 */ 299#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 300#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 301 302/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 303#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 304 OR_SCY_5_CLK | OR_EHTR) 305 306#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 307#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 308#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 309 310#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 311#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 312#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 313 314/* 315 * BR2/3 and OR2/3 (SDRAM) 316 * 317 */ 318#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 319#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 320#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 321 322/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 323#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 324 325#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 326#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 327 328#ifndef CONFIG_CAN_DRIVER 329#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 330#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 331#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 332#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 333#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 334#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 335#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 336 BR_PS_8 | BR_MS_UPMB | BR_V ) 337#endif /* CONFIG_CAN_DRIVER */ 338 339/* 340 * Memory Periodic Timer Prescaler 341 */ 342 343/* periodic timer for refresh */ 344#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 345 346/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 347#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 348#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 349 350/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 351#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 352#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 353 354/* 355 * MAMR settings for SDRAM 356 */ 357 358/* 8 column SDRAM */ 359#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 360 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 361 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 362/* 9 column SDRAM */ 363#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 364 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 365 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 366 367/* pass open firmware flat tree */ 368#define CONFIG_OF_LIBFDT 1 369#define CONFIG_OF_BOARD_SETUP 1 370#define CONFIG_HWCONFIG 1 371 372#endif /* __CONFIG_H */ 373