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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_ARIA 1
32
33
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45
46
47
48
49#define CONFIG_E300 1
50#define CONFIG_MPC512X 1
51#define CONFIG_FSL_DIU_FB 1
52
53#define CONFIG_SYS_TEXT_BASE 0xFFF00000
54
55
56#undef CONFIG_VIDEO
57
58#if defined(CONFIG_VIDEO)
59#define CONFIG_CFB_CONSOLE
60#define CONFIG_VGA_AS_SINGLE_DEVICE
61#endif
62
63
64
65#define CONFIG_SYS_MPC512X_CLKIN 33000000
66
67#define CONFIG_BOARD_EARLY_INIT_F
68#define CONFIG_MISC_INIT_R
69
70#define CONFIG_SYS_IMMR 0x80000000
71#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
72
73#define CONFIG_SYS_MEMTEST_START 0x00200000
74#define CONFIG_SYS_MEMTEST_END 0x00400000
75
76
77
78
79#define CONFIG_SYS_DDR_SIZE 256
80#define CONFIG_SYS_DDR_BASE 0x00000000
81#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
82#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
83
84#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
85
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129
130#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | \
131 (1 << 30) | \
132 (1 << 29) | \
133 (0 << 28) | \
134 (4 << 25) | \
135 (3 << 21) | \
136 (0 << 18) | \
137 (0 << 17) | \
138 (2 << 13) | \
139 (0 << 12) | \
140 (1 << 11) | \
141 (2 << 8) | \
142 (0 << 7) | \
143 (1 << 6) | \
144 (0 << 5) | \
145 (0 << 4) | \
146 (0 << 1) | \
147 (0 << 0) \
148 )
149
150#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
151#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
152#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
153
154#define CONFIG_SYS_DDRCMD_NOP 0x01380000
155#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
156#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | \
157 (0 << 22) | \
158 (0 << 21) | \
159 (0 << 20) | \
160 (0 << 19) | \
161 (1 << 16) | \
162 (0 << 15) | \
163 (0 << 12) | \
164 (0 << 11) | \
165 (0 << 10) | \
166 (0 << 7) | \
167 (0 << 6) | \
168 (0 << 3) | \
169 (0 << 2) | \
170 (1 << 1) | \
171 (0 << 0) \
172 )
173#define CONFIG_SYS_MICRON_EMR2 0x01020000
174#define CONFIG_SYS_MICRON_EMR3 0x01030000
175#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
176#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
177#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | \
178 (0 << 22) | \
179 (0 << 21) | \
180 (0 << 20) | \
181 (0 << 19) | \
182 (1 << 16) | \
183 (0 << 15) | \
184 (0 << 12) | \
185 (0 << 11) | \
186 (1 << 10) | \
187 (7 << 7) | \
188 (0 << 6) | \
189 (0 << 3) | \
190 (1 << 2) | \
191 (0 << 1) | \
192 (0 << 0) \
193 )
194
195
196
197
198
199#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
200#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
201#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
202#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
203
204
205#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
206#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
207#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
208#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
209#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
210#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
211#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
212#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
213#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
214#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
215#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
216#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
217#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
218#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
219#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
220#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
221#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
222#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
223#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
224#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
225#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
226#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
227#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
228
229
230
231
232#define CONFIG_SYS_FLASH_CFI
233#define CONFIG_FLASH_CFI_DRIVER
234#define CONFIG_SYS_FLASH_BASE 0xF8000000
235#define CONFIG_SYS_FLASH_SIZE 0x08000000
236
237#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
238#define CONFIG_SYS_MAX_FLASH_BANKS 1
239#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
240#define CONFIG_SYS_MAX_FLASH_SECT 1024
241
242#undef CONFIG_SYS_FLASH_CHECKSUM
243
244
245
246
247
248#define CONFIG_CMD_NAND
249#define CONFIG_JFFS2_NAND
250
251
252#define CONFIG_NAND_MPC5121_NFC
253#define CONFIG_SYS_NAND_BASE 0x40000000
254
255#define CONFIG_SYS_MAX_NAND_DEVICE 1
256#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
257
258
259
260
261#define CONFIG_FSL_NFC_WIDTH 1
262#define CONFIG_FSL_NFC_WRITE_SIZE 2048
263#define CONFIG_FSL_NFC_SPARE_SIZE 64
264#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
265
266#define CONFIG_SYS_SRAM_BASE 0x30000000
267#define CONFIG_SYS_SRAM_SIZE 0x00020000
268
269
270#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
271 CONFIG_SYS_SRAM_SIZE)
272#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000
273
274#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
275 CONFIG_SYS_ARIA_SRAM_SIZE)
276#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000
277
278#define CONFIG_SYS_CS0_CFG 0x05059150
279#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
280 (5 << 16) | \
281 (1 << 15) | \
282 (0 << 14) | \
283 (0 << 13) | \
284 (1 << 12) | \
285 (0 << 10) | \
286 (3 << 8) | \
287 (0 << 7) | \
288 (1 << 6) | \
289 (1 << 4) | \
290 (0 << 3) | \
291 (0 << 2) | \
292 (0 << 1) | \
293 (0 << 0) \
294 )
295#define CONFIG_SYS_CS6_CFG 0x05059150
296
297
298#define CONFIG_SYS_CS_ALETIMING 0x00000005
299
300
301#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
302#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
303
304#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
305 GENERATED_GBL_DATA_SIZE)
306#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
307
308#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
309#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
310
311#ifdef CONFIG_FSL_DIU_FB
312#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
313#else
314#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
315#endif
316
317
318#define CONFIG_ARIA_FPGA 1
319
320
321
322
323#define CONFIG_CONS_INDEX 1
324
325
326
327
328#define CONFIG_PSC_CONSOLE 3
329#if CONFIG_PSC_CONSOLE != 3
330#error CONFIG_PSC_CONSOLE must be 3
331#endif
332
333#define CONFIG_BAUDRATE 115200
334#define CONFIG_SYS_BAUDRATE_TABLE \
335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
336
337#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
338#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
339#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
340#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
341
342#define CONFIG_CMDLINE_EDITING 1
343
344#define CONFIG_SYS_HUSH_PARSER
345#ifdef CONFIG_SYS_HUSH_PARSER
346#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
347#endif
348
349
350
351
352#ifdef CONFIG_PCI
353
354#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
355#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
356#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
357#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
358 CONFIG_SYS_PCI_MEM_SIZE)
359#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
360#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
361#define CONFIG_SYS_PCI_IO_BASE 0x00000000
362#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
363#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
364
365#define CONFIG_PCI_PNP
366
367#define CONFIG_PCI_SCAN_SHOW
368
369#endif
370
371
372#define CONFIG_HARD_I2C
373#undef CONFIG_SOFT_I2C
374#define CONFIG_I2C_MULTI_BUS
375
376
377#define CONFIG_SYS_I2C_SPEED 100000
378#define CONFIG_SYS_I2C_SLAVE 0x7F
379#if 0
380#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}
381#endif
382
383
384
385
386#undef CONFIG_IIM
387
388
389
390
391
392#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
393#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
394#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
395#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
396
397
398
399
400#define CONFIG_MPC512x_FEC 1
401#define CONFIG_PHY_ADDR 0x17
402#define CONFIG_MII 1
403#define CONFIG_FEC_AN_TIMEOUT 1
404#define CONFIG_HAS_ETH0
405
406
407
408
409#define CONFIG_ENV_IS_IN_FLASH 1
410
411#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
412 CONFIG_SYS_MONITOR_LEN)
413#define CONFIG_ENV_SIZE 0x2000
414#define CONFIG_ENV_SECT_SIZE 0x20000
415
416
417#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
418 CONFIG_ENV_SECT_SIZE)
419#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
420
421#define CONFIG_LOADS_ECHO 1
422#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
423
424#include <config_cmd_default.h>
425
426#define CONFIG_CMD_ASKENV
427#define CONFIG_CMD_DHCP
428#define CONFIG_CMD_EEPROM
429#undef CONFIG_CMD_FUSE
430#define CONFIG_CMD_I2C
431#undef CONFIG_CMD_IDE
432#define CONFIG_CMD_JFFS2
433#define CONFIG_CMD_MII
434#define CONFIG_CMD_NFS
435#define CONFIG_CMD_PING
436#define CONFIG_CMD_REGINFO
437
438#if defined(CONFIG_PCI)
439#define CONFIG_CMD_PCI
440#endif
441
442#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
443#define CONFIG_DOS_PARTITION
444#define CONFIG_MAC_PARTITION
445#define CONFIG_ISO_PARTITION
446#endif
447
448
449
450
451#define CONFIG_CMD_MTDPARTS
452#define CONFIG_MTD_DEVICE
453#define CONFIG_FLASH_CFI_MTD
454#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
455
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465
466
467#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
468 "16m(rootfs)," \
469 "4m(kernel)," \
470 "768k(u-boot)," \
471 "256k(dtb);" \
472 "mpc5121.nand:-(data)"
473
474
475
476
477
478
479
480
481#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
482
483
484
485
486#define CONFIG_SYS_LONGHELP
487#define CONFIG_SYS_LOAD_ADDR 0x2000000
488#define CONFIG_SYS_PROMPT "=> "
489
490#ifdef CONFIG_CMD_KGDB
491# define CONFIG_SYS_CBSIZE 1024
492#else
493# define CONFIG_SYS_CBSIZE 256
494#endif
495
496
497#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
498 sizeof(CONFIG_SYS_PROMPT) + 16)
499
500#define CONFIG_SYS_MAXARGS 32
501
502#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
503
504#define CONFIG_SYS_HZ 1000
505
506
507
508
509
510
511#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
512
513
514#define CONFIG_SYS_DCACHE_SIZE 32768
515#define CONFIG_SYS_CACHELINE_SIZE 32
516#ifdef CONFIG_CMD_KGDB
517#define CONFIG_SYS_CACHELINE_SHIFT 5
518#endif
519
520#define CONFIG_SYS_HID0_INIT 0x000000000
521#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
522 HID0_ICE)
523#define CONFIG_SYS_HID2 HID2_HBE
524
525#define CONFIG_HIGH_BATS 1
526
527#ifdef CONFIG_CMD_KGDB
528#define CONFIG_KGDB_BAUDRATE 230400
529#define CONFIG_KGDB_SER_INDEX 2
530#endif
531
532
533
534
535#define CONFIG_ENV_OVERWRITE
536#define CONFIG_TIMESTAMP
537
538#define CONFIG_HOSTNAME aria
539#define CONFIG_BOOTFILE "aria/uImage"
540#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
541
542#define CONFIG_LOADADDR 400000
543
544#define CONFIG_BOOTDELAY 5
545#undef CONFIG_BOOTARGS
546
547#define CONFIG_BAUDRATE 115200
548
549#define CONFIG_PREBOOT "echo;" \
550 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
551 "echo"
552
553#define CONFIG_EXTRA_ENV_SETTINGS \
554 "u-boot_addr_r=200000\0" \
555 "kernel_addr_r=600000\0" \
556 "fdt_addr_r=880000\0" \
557 "ramdisk_addr_r=900000\0" \
558 "u-boot_addr=FFF00000\0" \
559 "kernel_addr=FFB00000\0" \
560 "fdt_addr=FFFC0000\0" \
561 "ramdisk_addr=FEB00000\0" \
562 "ramdiskfile=aria/uRamdisk\0" \
563 "u-boot=aria/u-boot.bin\0" \
564 "fdtfile=aria/aria.dtb\0" \
565 "netdev=eth0\0" \
566 "consdev=ttyPSC0\0" \
567 "nfsargs=setenv bootargs root=/dev/nfs rw " \
568 "nfsroot=${serverip}:${rootpath}\0" \
569 "ramargs=setenv bootargs root=/dev/ram rw\0" \
570 "addip=setenv bootargs ${bootargs} " \
571 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
572 ":${hostname}:${netdev}:off panic=1\0" \
573 "addtty=setenv bootargs ${bootargs} " \
574 "console=${consdev},${baudrate}\0" \
575 "flash_nfs=run nfsargs addip addtty;" \
576 "bootm ${kernel_addr} - ${fdt_addr}\0" \
577 "flash_self=run ramargs addip addtty;" \
578 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
579 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
580 "tftp ${fdt_addr_r} ${fdtfile};" \
581 "run nfsargs addip addtty;" \
582 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
583 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
584 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
585 "tftp ${fdt_addr_r} ${fdtfile};" \
586 "run ramargs addip addtty;" \
587 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
588 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
589 "update=protect off ${u-boot_addr} +${filesize};" \
590 "era ${u-boot_addr} +${filesize};" \
591 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
592 "upd=run load update\0" \
593 ""
594
595#define CONFIG_BOOTCOMMAND "run flash_self"
596
597#define CONFIG_OF_LIBFDT 1
598#define CONFIG_OF_BOARD_SETUP 1
599#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
600
601#define OF_CPU "PowerPC,5121@0"
602#define OF_SOC_COMPAT "fsl,mpc5121-immr"
603#define OF_TBCLK (bd->bi_busfreq / 4)
604#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
605
606
607
608
609
610
611#undef CONFIG_IDE_8xx_PCCARD
612#undef CONFIG_IDE_8xx_DIRECT
613#undef CONFIG_IDE_LED
614
615#define CONFIG_IDE_RESET
616#define CONFIG_IDE_PREINIT
617
618#define CONFIG_SYS_IDE_MAXBUS 1
619#define CONFIG_SYS_IDE_MAXDEVICE 2
620
621#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
622#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
623
624
625#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
626
627
628#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
629
630
631#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
632
633
634#define CONFIG_SYS_ATA_STRIDE 4
635
636#define ATA_BASE_ADDR get_pata_base()
637
638
639
640
641#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
642#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
643#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
644#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
645#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
646#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
647#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
648#define FSL_ATA_CTRL_IORDY_EN 0x01000000
649
650#endif
651