LXR uboot/include/configs/dig297.h

   1/*
   2 * (C) Copyright 2011 Comelit Group SpA
   3 * Luca Ceresoli <luca.ceresoli@comelit.it>
   4 *
   5 * Based on omap3_beagle.h:
   6 * (C) Copyright 2006-2008
   7 * Texas Instruments.
   8 * Richard Woodruff <r-woodruff2@ti.com>
   9 * Syed Mohammed Khasim <x0khasim@ti.com>
  10 *
  11 * Configuration settings for the Comelit DIG297 board.
  12 *
  13 * See file CREDITS for list of people who contributed to this
  14 * project.
  15 *
  16 * This program is free software; you can redistribute it and/or
  17 * modify it under the terms of the GNU General Public License as
  18 * published by the Free Software Foundation; either version 2 of
  19 * the License, or (at your option) any later version.
  20 *
  21 * This program is distributed in the hope that it will be useful,
  22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24 * GNU General Public License for more details.
  25 *
  26 * You should have received a copy of the GNU General Public License
  27 * along with this program; if not, write to the Free Software
  28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29 * MA 02111-1307 USA
  30 */
  31
  32#ifndef __CONFIG_H
  33#define __CONFIG_H
  34
  35#include <asm/mach-types.h>
  36#ifdef MACH_TYPE_OMAP3_CPS
  37#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
  38#else
  39#define MACH_TYPE_OMAP3_CPS 2751
  40#endif
  41#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
  42
  43/*
  44 * High Level Configuration Options
  45 */
  46#define CONFIG_OMAP             /* in a TI OMAP core */
  47#define CONFIG_OMAP34XX         /* which is a 34XX */
  48
  49#define CONFIG_SYS_TEXT_BASE    0x80008000
  50
  51#define CONFIG_SDRC     /* The chip has SDRC controller */
  52
  53#include <asm/arch/cpu.h>               /* get chip and board defs */
  54#include <asm/arch/omap3.h>
  55
  56/*
  57 * Display CPU and Board information
  58 */
  59#define CONFIG_DISPLAY_CPUINFO
  60#define CONFIG_DISPLAY_BOARDINFO
  61
  62/* Clock Defines */
  63#define V_OSCK                  26000000        /* Clock output from T2 */
  64#define V_SCLK                  (V_OSCK >> 1)
  65
  66#undef CONFIG_USE_IRQ                           /* no support for IRQs */
  67#define CONFIG_MISC_INIT_R
  68
  69#define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  70#define CONFIG_SETUP_MEMORY_TAGS
  71#define CONFIG_INITRD_TAG
  72#define CONFIG_REVISION_TAG
  73
  74/*
  75 * Size of malloc() pool
  76 */
  77#define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  78                                                /* Sector */
  79#define CONFIG_SYS_MALLOC_LEN           (1024 << 10) /* UBI needs >= 512 kB */
  80
  81/*
  82 * Hardware drivers
  83 */
  84
  85/*
  86 * NS16550 Configuration
  87 */
  88#define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  89
  90#define CONFIG_SYS_NS16550
  91#define CONFIG_SYS_NS16550_SERIAL
  92#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  93#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  94
  95/*
  96 * select serial console configuration: UART3 (ttyO2)
  97 */
  98#define CONFIG_CONS_INDEX               3
  99#define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
 100#define CONFIG_SERIAL3                  3
 101
 102/* allow to overwrite serial and ethaddr */
 103#define CONFIG_ENV_OVERWRITE
 104#define CONFIG_BAUDRATE                 115200
 105#define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
 106                                        115200}
 107#define CONFIG_GENERIC_MMC              1
 108#define CONFIG_MMC                      1
 109#define CONFIG_OMAP_HSMMC               1
 110#define CONFIG_DOS_PARTITION
 111
 112/* DDR - I use Micron DDR */
 113#define CONFIG_OMAP3_MICRON_DDR
 114
 115/* library portions to compile in */
 116#define CONFIG_RBTREE
 117#define CONFIG_MTD_PARTITIONS
 118#define CONFIG_LZO
 119
 120/* commands to include */
 121#include <config_cmd_default.h>
 122
 123#define CONFIG_CMD_FAT          /* FAT support                  */
 124#define CONFIG_CMD_UBI          /* UBI Support                  */
 125#define CONFIG_CMD_UBIFS        /* UBIFS Support                */
 126#define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands    */
 127#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 128#define MTDIDS_DEFAULT          "nand0=omap2-nand.0"
 129#define MTDPARTS_DEFAULT        "mtdparts=omap2-nand.0:896k(uboot),"\
 130                                "128k(uboot-env),3m(kernel),252m(ubi)"
 131
 132#define CONFIG_CMD_I2C          /* I2C serial bus support       */
 133#define CONFIG_CMD_MMC          /* MMC support                  */
 134#define CONFIG_CMD_NAND         /* NAND support                 */
 135
 136#undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 137#undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 138#undef CONFIG_CMD_IMI           /* iminfo                       */
 139#undef CONFIG_CMD_IMLS          /* List all found images        */
 140#define CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot    */
 141#undef CONFIG_CMD_NFS           /* NFS support                  */
 142
 143#define CONFIG_SYS_NO_FLASH
 144#define CONFIG_HARD_I2C
 145#define CONFIG_SYS_I2C_SPEED            100000
 146#define CONFIG_SYS_I2C_SLAVE            1
 147#define CONFIG_SYS_I2C_BUS              0
 148#define CONFIG_SYS_I2C_BUS_SELECT       1
 149#define CONFIG_DRIVER_OMAP34XX_I2C      1
 150
 151/*
 152 * TWL4030
 153 */
 154#define CONFIG_TWL4030_POWER
 155#define CONFIG_TWL4030_LED
 156
 157/*
 158 * Board NAND Info.
 159 */
 160#define CONFIG_NAND_OMAP_GPMC
 161#define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 162                                                        /* to access nand */
 163#define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 164                                                        /* to access nand at */
 165                                                        /* CS0 */
 166#define GPMC_NAND_ECC_LP_x16_LAYOUT
 167
 168#define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 169
 170#if defined(CONFIG_CMD_NET)
 171/*
 172 * SMSC9220 Ethernet
 173 */
 174
 175#define CONFIG_SMC911X
 176#define CONFIG_SMC911X_32_BIT
 177#define CONFIG_SMC911X_BASE     0x2C000000
 178
 179#endif /* (CONFIG_CMD_NET) */
 180
 181/* Environment information */
 182#define CONFIG_BOOTDELAY                1
 183
 184#define CONFIG_EXTRA_ENV_SETTINGS \
 185        "loadaddr=0x82000000\0" \
 186        "console=ttyO2,115200n8\0" \
 187        "mtdids=" MTDIDS_DEFAULT "\0" \
 188        "mtdparts=" MTDPARTS_DEFAULT "\0" \
 189        "partition=nand0,3\0"\
 190        "mmcroot=/dev/mmcblk0p2 rw\0" \
 191        "mmcrootfstype=ext3 rootwait\0" \
 192        "nandroot=ubi0:rootfs ro\0" \
 193        "nandrootfstype=ubifs\0" \
 194        "nfspath=/srv/nfs\0" \
 195        "tftpfilename=uImage\0" \
 196        "gatewayip=0.0.0.0\0" \
 197        "mmcargs=setenv bootargs console=${console} " \
 198                "${mtdparts} " \
 199                "root=${mmcroot} " \
 200                "rootfstype=${mmcrootfstype} " \
 201                "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 202                        "${netmask}:${hostname}::off\0" \
 203        "nandargs=setenv bootargs console=${console} " \
 204                "${mtdparts} " \
 205                "ubi.mtd=3 " \
 206                "root=${nandroot} " \
 207                "rootfstype=${nandrootfstype} " \
 208                "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 209                        "${netmask}:${hostname}::off\0" \
 210        "netargs=setenv bootargs console=${console} " \
 211                "${mtdparts} " \
 212                "root=/dev/nfs rw " \
 213                "nfsroot=${serverip}:${nfspath} " \
 214                "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 215                        "${netmask}:${hostname}::off\0" \
 216        "mmcboot=echo Booting from mmc ...; " \
 217                "run mmcargs; " \
 218                "bootm ${loadaddr}\0" \
 219        "nandboot=echo Booting from nand ...; " \
 220                "run nandargs; " \
 221                "nand read ${loadaddr} 100000 300000; " \
 222                "bootm ${loadaddr}\0" \
 223        "netboot=echo Booting from network ...; " \
 224                "run netargs; " \
 225                "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
 226                "bootm ${loadaddr}\0" \
 227        "resetenv=nand erase e0000 20000\0"\
 228
 229#define CONFIG_BOOTCOMMAND \
 230        "run nandboot"
 231
 232#define CONFIG_AUTO_COMPLETE
 233/*
 234 * Miscellaneous configurable options
 235 */
 236#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 237#define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 238#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 239#define CONFIG_SYS_PROMPT               "DIG297# "
 240#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 241/* Print Buffer Size */
 242#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 243                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 244#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 245/* Boot Argument Buffer Size */
 246#define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 247
 248#define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 249                                                                /* works on */
 250#define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 251                                        0x01F00000) /* 31MB */
 252
 253#define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 254                                                        /* load address */
 255
 256/*
 257 * OMAP3 has 12 GP timers, they can be driven by the system clock
 258 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 259 * This rate is divided by a local divisor.
 260 */
 261#define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 262#define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 263#define CONFIG_SYS_HZ                   1000
 264
 265/*-----------------------------------------------------------------------
 266 * Stack sizes
 267 *
 268 * The stack sizes are set up in start.S using the settings below
 269 */
 270#define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
 271#ifdef CONFIG_USE_IRQ
 272#define CONFIG_STACKSIZE_IRQ    (4 << 10)       /* IRQ stack 4 KiB */
 273#define CONFIG_STACKSIZE_FIQ    (4 << 10)       /* FIQ stack 4 KiB */
 274#endif
 275
 276/*-----------------------------------------------------------------------
 277 * Physical Memory Map
 278 */
 279#define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 280#define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 281#define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 282#define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 283
 284/*-----------------------------------------------------------------------
 285 * FLASH and environment organization
 286 */
 287
 288/* **** PISMO SUPPORT *** */
 289
 290/* Configure the PISMO */
 291#define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 292
 293#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 294
 295#define CONFIG_SYS_FLASH_BASE           boot_flash_base
 296
 297/* Monitor at start of flash */
 298#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 299
 300#define CONFIG_ENV_IS_IN_NAND
 301#define SMNAND_ENV_OFFSET               0x0E0000 /* environment starts here */
 302
 303#define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 304#define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 305#define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 306
 307#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 308#define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 309#define CONFIG_SYS_INIT_RAM_SIZE        0x800
 310#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 311                                         CONFIG_SYS_INIT_RAM_SIZE - \
 312                                         GENERATED_GBL_DATA_SIZE)
 313
 314#endif /* __CONFIG_H */
 315