1/* 2 * (C) Copyright 2008 3 * Graeme Russ, graeme.russ@gmail.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#include <asm/ibmpc.h> 25/* 26 * board/config.h - configuration options, board specific 27 */ 28 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32/* 33 * High Level Configuration Options 34 * (easy to change) 35 */ 36#define CONFIG_SYS_SC520 37#define CONFIG_SYS_SC520_SSI 38#define CONFIG_SHOW_BOOT_PROGRESS 39#define CONFIG_LAST_STAGE_INIT 40 41/*----------------------------------------------------------------------- 42 * Watchdog Configuration 43 * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the 44 * bottom (processor) board MUST be removed! 45 */ 46#undef CONFIG_WATCHDOG 47#define CONFIG_HW_WATCHDOG 48 49/*----------------------------------------------------------------------- 50 * Real Time Clock Configuration 51 */ 52#define CONFIG_RTC_MC146818 53#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 54 55/*----------------------------------------------------------------------- 56 * Serial Configuration 57 */ 58#define CONFIG_SERIAL_MULTI 59#define CONFIG_CONS_INDEX 1 60#define CONFIG_SYS_NS16550 61#define CONFIG_SYS_NS16550_SERIAL 62#define CONFIG_SYS_NS16550_REG_SIZE 1 63#define CONFIG_SYS_NS16550_CLK 1843200 64#define CONFIG_BAUDRATE 9600 65#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \ 66 9600, 19200, 38400, 115200} 67#define CONFIG_SYS_NS16550_COM1 UART0_BASE 68#define CONFIG_SYS_NS16550_COM2 UART1_BASE 69#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) 70#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) 71#define CONFIG_SYS_NS16550_PORT_MAPPED 72 73/*----------------------------------------------------------------------- 74 * Video Configuration 75 */ 76#undef CONFIG_VIDEO 77#undef CONFIG_CFB_CONSOLE 78 79/*----------------------------------------------------------------------- 80 * Command line configuration. 81 */ 82#include <config_cmd_default.h> 83 84#define CONFIG_CMD_BDI 85#define CONFIG_CMD_BOOTD 86#define CONFIG_CMD_CONSOLE 87#define CONFIG_CMD_DATE 88#define CONFIG_CMD_ECHO 89#define CONFIG_CMD_FLASH 90#define CONFIG_CMD_FPGA 91#define CONFIG_CMD_IMI 92#define CONFIG_CMD_IMLS 93#define CONFIG_CMD_IRQ 94#define CONFIG_CMD_ITEST 95#define CONFIG_CMD_LOADB 96#define CONFIG_CMD_LOADS 97#define CONFIG_CMD_MEMORY 98#define CONFIG_CMD_MISC 99#define CONFIG_CMD_NET 100#undef CONFIG_CMD_NFS 101#define CONFIG_CMD_PCI 102#define CONFIG_CMD_PING 103#define CONFIG_CMD_RUN 104#define CONFIG_CMD_SAVEENV 105#define CONFIG_CMD_SETGETDCR 106#define CONFIG_CMD_SOURCE 107#define CONFIG_CMD_XIMG 108#define CONFIG_CMD_ZBOOT 109 110#define CONFIG_BOOTDELAY 15 111#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" 112 113#if defined(CONFIG_CMD_KGDB) 114#define CONFIG_KGDB_BAUDRATE 115200 115#define CONFIG_KGDB_SER_INDEX 2 116#endif 117 118/* 119 * Miscellaneous configurable options 120 */ 121#define CONFIG_SYS_LONGHELP 122#define CONFIG_SYS_PROMPT "boot > " 123#define CONFIG_SYS_CBSIZE 256 124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 125 sizeof(CONFIG_SYS_PROMPT) + \ 126 16) 127#define CONFIG_SYS_MAXARGS 16 128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 129 130#define CONFIG_SYS_MEMTEST_START 0x00100000 131#define CONFIG_SYS_MEMTEST_END 0x01000000 132#define CONFIG_SYS_LOAD_ADDR 0x100000 133#define CONFIG_SYS_HZ 1000 134 135/*----------------------------------------------------------------------- 136 * SDRAM Configuration 137 */ 138#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 139#define CONFIG_SYS_SDRAM_REFRESH_RATE 156 140#define CONFIG_NR_DRAM_BANKS 4 141 142/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ 143#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY 144#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY 145#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T 146#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T 147 148/*----------------------------------------------------------------------- 149 * CPU Features 150 */ 151#define CONFIG_SYS_SC520_HIGH_SPEED 0 152#define CONFIG_SYS_SC520_RESET 153#define CONFIG_SYS_SC520_TIMER 154#undef CONFIG_SYS_GENERIC_TIMER 155#define CONFIG_SYS_PCAT_INTERRUPTS 156#define CONFIG_SYS_NUM_IRQS 16 157#define CONFIG_SYS_PC_BIOS 158#define CONFIG_SYS_PCI_BIOS 159#define CONFIG_SYS_X86_REALMODE 160#define CONFIG_SYS_X86_ISR_TIMER 161 162/*----------------------------------------------------------------------- 163 * Memory organization: 164 * 32kB Stack 165 * 16kB Cache-As-RAM @ 0x19200000 166 * 256kB Monitor 167 * (128kB + Environment Sector Size) malloc pool 168 */ 169#define CONFIG_SYS_STACK_SIZE (32 * 1024) 170#define CONFIG_SYS_CAR_ADDR 0x19200000 171#define CONFIG_SYS_CAR_SIZE (16 * 1024) 172#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \ 173 CONFIG_SYS_CAR_SIZE) 174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 175#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 176#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \ 177 128*1024) 178/* Address of temporary Global Data */ 179#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR 180 181 182/* allow to overwrite serial and ethaddr */ 183#define CONFIG_ENV_OVERWRITE 184 185/*----------------------------------------------------------------------- 186 * FLASH configuration 187 * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000) 188 * 16MB StrataFlash #1 @ 0x10000000 189 * 16MB StrataFlash #2 @ 0x11000000 190 */ 191#define CONFIG_FLASH_CFI_DRIVER 192#define CONFIG_FLASH_CFI_LEGACY 193#define CONFIG_SYS_FLASH_CFI 194#define CONFIG_SYS_MAX_FLASH_BANKS 3 195#define CONFIG_SYS_FLASH_BASE 0x38000000 196#define CONFIG_SYS_FLASH_BASE_1 0x10000000 197#define CONFIG_SYS_FLASH_BASE_2 0x11000000 198#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 199 CONFIG_SYS_FLASH_BASE_1, \ 200 CONFIG_SYS_FLASH_BASE_2} 201#define CONFIG_SYS_FLASH_EMPTY_INFO 202#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 203#define CONFIG_SYS_MAX_FLASH_SECT 128 204#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 205#define CONFIG_SYS_FLASH_LEGACY_512Kx8 206#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */ 207#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */ 208 209/*----------------------------------------------------------------------- 210 * Environment configuration 211 * - Boot flash is 512kB with 64kB sectors 212 * - StrataFlash is 32MB with 128kB sectors 213 * - Redundant embedded environment is 25% of the Boot flash 214 * - Redundant StrataFlash environment is <1% of the StrataFlash 215 * - Environment is therefore located in StrataFlash 216 * - Primary copy is located in first sector of first flash 217 * - Redundant copy is located in second sector of first flash 218 * - Stack is only 32kB, so environment size is limited to 4kB 219 */ 220#define CONFIG_ENV_IS_IN_FLASH 221#define CONFIG_ENV_SECT_SIZE 0x20000 222#define CONFIG_ENV_SIZE 0x01000 223#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 224#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ 225 CONFIG_ENV_SECT_SIZE) 226#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 227 228/*----------------------------------------------------------------------- 229 * PCI configuration 230 */ 231#define CONFIG_PCI 232#define CONFIG_PCI_PNP 233#define CONFIG_SYS_FIRST_PCI_IRQ 10 234#define CONFIG_SYS_SECOND_PCI_IRQ 9 235#define CONFIG_SYS_THIRD_PCI_IRQ 11 236#define CONFIG_SYS_FORTH_PCI_IRQ 15 237 238/*----------------------------------------------------------------------- 239 * Network device (TRL8100B) support 240 */ 241#define CONFIG_RTL8139 242 243/*----------------------------------------------------------------------- 244 * BOOTCS Control (for AM29LV040B-120JC) 245 * 246 * 000 0 00 0 000 11 0 011 }- 0x0033 247 * \ / | \| | \ / \| | \ / 248 * | | | | | | | | 249 * | | | | | | | +---- 3 Wait States (First Access) 250 * | | | | | | +------- Reserved 251 * | | | | | +--------- 3 Wait States (Subsequent Access) 252 * | | | | +------------- Reserved 253 * | | | +---------------- Non-Paged Mode 254 * | | +------------------ 8 Bit Wide 255 * | +--------------------- GP Bus 256 * +------------------------ Reserved 257 */ 258#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033 259 260/*----------------------------------------------------------------------- 261 * ROMCS Control (for E28F128J3A-150 StrataFlash) 262 * 263 * 000 0 01 1 000 01 0 101 }- 0x0615 264 * \ / | \| | \ / \| | \ / 265 * | | | | | | | | 266 * | | | | | | | +---- 5 Wait States (First Access) 267 * | | | | | | +------- Reserved 268 * | | | | | +--------- 1 Wait State (Subsequent Access) 269 * | | | | +------------- Reserved 270 * | | | +---------------- Paged Mode 271 * | | +------------------ 16 Bit Wide 272 * | +--------------------- GP Bus 273 * +------------------------ Reserved 274 */ 275#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 276#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615 277 278/*----------------------------------------------------------------------- 279 * SC520 General Purpose Bus configuration 280 * 281 * Chip Select Offset 1 Clock Cycle 282 * Chip Select Pulse Width 8 Clock Cycles 283 * Chip Select Read Offset 2 Clock Cycles 284 * Chip Select Read Width 6 Clock Cycles 285 * Chip Select Write Offset 2 Clock Cycles 286 * Chip Select Write Width 6 Clock Cycles 287 * Chip Select Recovery Time 2 Clock Cycles 288 * 289 * Timing Diagram (from SC520 Register Set Manual - Order #22005B) 290 * 291 * |<-------------General Purpose Bus Cycle---------------->| 292 * | | 293 * ----------------------\__________________/------------------ 294 * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> | 295 * 296 * ------------------------\_______________/------------------- 297 * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->| 298 * 299 * --------------------------\_______________/----------------- 300 * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->| 301 * 302 * ________/-----------\_______________________________________ 303 * |<--->|<--------->| 304 * ^ ^ 305 * (GPALEOFF + 1) | 306 * | 307 * (GPALEW + 1) 308 */ 309#define CONFIG_SYS_SC520_GPCSOFF 0x00 310#define CONFIG_SYS_SC520_GPCSPW 0x07 311#define CONFIG_SYS_SC520_GPRDOFF 0x01 312#define CONFIG_SYS_SC520_GPRDW 0x05 313#define CONFIG_SYS_SC520_GPWROFF 0x01 314#define CONFIG_SYS_SC520_GPWRW 0x05 315#define CONFIG_SYS_SC520_GPCSRT 0x01 316 317/*----------------------------------------------------------------------- 318 * SC520 Programmable I/O configuration 319 * 320 * Pin Mode Dir. Description 321 * ---------------------------------------------------------------------- 322 * PIO0 PIO Output Unused 323 * PIO1 GPBHE# Output GP Bus Byte High Enable (active low) 324 * PIO2 PIO Output Auxiliary power output enable 325 * PIO3 GPAEN Output GP Bus Address Enable 326 * PIO4 PIO Output Top Board Enable (active low) 327 * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode) 328 * PIO6 PIO Input Data output of Power Supply ADC 329 * PIO7 PIO Output Clock input to Power Supply ADC 330 * PIO8 PIO Output Chip Select input of Power Supply ADC 331 * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low) 332 * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low) 333 * PIO11 PIO Input StrataFlash 1 Status 334 * PIO12 PIO Input StrataFlash 2 Status 335 * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low) 336 * PIO14 PIO Input Low Input Voltage Warning (active low) 337 * PIO15 PIO Output Watchdog (must toggle at least every 1.6s) 338 * PIO16 PIO Input Power Fail 339 * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low) 340 * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low) 341 * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low) 342 * PIO20 GPIRQ3 Input UART D IRQ 343 * PIO21 GPIRQ2 Input UART C IRQ 344 * PIO22 GPIRQ1 Input UART B IRQ 345 * PIO23 GPIRQ0 Input UART A IRQ 346 * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable 347 * PIO25 PIO Input Battery OK Indication 348 * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access 349 * PIO27 GPCS0# Output SRAM 1 Chip Select 350 * PIO28 PIO Input Top Board UART CTS 351 * PIO29 PIO Output FPGA Program Mode (active low) 352 * PIO30 PIO Input FPGA Initialised (active low) 353 * PIO31 PIO Input FPGA Done (active low) 354 */ 355#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a 356#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe 357#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf 358#define CONFIG_SYS_SC520_PIODIR31_16 0x2900 359 360/*----------------------------------------------------------------------- 361 * PIO Pin defines 362 */ 363#define CONFIG_SYS_ENET_AUX_PWR 0x0004 364#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010 365#define CONFIG_SYS_ENET_SF_WIDTH 0x0020 366#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040 367#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080 368#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100 369#define CONFIG_SYS_ENET_SF1_MODE 0x0200 370#define CONFIG_SYS_ENET_SF2_MODE 0x0400 371#define CONFIG_SYS_ENET_SF1_STATUS 0x0800 372#define CONFIG_SYS_ENET_SF2_STATUS 0x1000 373#define CONFIG_SYS_ENET_PWR_STATUS 0x4000 374#define CONFIG_SYS_ENET_WATCHDOG 0x8000 375 376#define CONFIG_SYS_ENET_PWR_FAIL 0x0001 377#define CONFIG_SYS_ENET_BAT_OK 0x0200 378#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000 379#define CONFIG_SYS_ENET_FPGA_PROG 0x2000 380#define CONFIG_SYS_ENET_FPGA_INIT 0x4000 381#define CONFIG_SYS_ENET_FPGA_DONE 0x8000 382 383/*----------------------------------------------------------------------- 384 * Chip Select Pin Function Select 385 * 386 * 1 1 1 1 1 0 0 0 }- 0xf8 387 * | | | | | | | | 388 * | | | | | | | +--- Reserved 389 * | | | | | | +----- GPCS1_SEL = ROMCS1# 390 * | | | | | +------- GPCS2_SEL = ROMCS2# 391 * | | | | +--------- GPCS3_SEL = GPCS3 392 * | | | +----------- GPCS4_SEL = GPCS4 393 * | | +------------- GPCS5_SEL = GPCS5 394 * | +--------------- GPCS6_SEL = GPCS6 395 * +----------------- GPCS7_SEL = GPCS7 396 */ 397#define CONFIG_SYS_SC520_CSPFS 0xf8 398 399/*----------------------------------------------------------------------- 400 * Clock Select (CLKTIMER[CLKTEST] pin) 401 * 402 * 0 111 00 1 0 }- 0x72 403 * | \ / \| | | 404 * | | | | +--- Pin Disabled 405 * | | | +----- Pin is an output 406 * | | +------- Reserved 407 * | +----------- Disabled (pin stays Low) 408 * +-------------- Reserved 409 */ 410#define CONFIG_SYS_SC520_CLKSEL 0x72 411 412/*----------------------------------------------------------------------- 413 * Address Decode Control 414 * 415 * 0 00 0 0 0 0 0 }- 0x00 416 * | \| | | | | | 417 * | | | | | | +--- Integrated UART 1 is enabled 418 * | | | | | +----- Integrated UART 2 is enabled 419 * | | | | +------- Integrated RTC is enabled 420 * | | | +--------- Reserved 421 * | | +----------- I/O Hole accesses are forwarded to the external GP bus 422 * | +------------- Reserved 423 * +---------------- Write-protect violations do not generate an IRQ 424 */ 425#define CONFIG_SYS_SC520_ADDDECCTL 0x00 426 427/*----------------------------------------------------------------------- 428 * UART Control 429 * 430 * 00000 1 1 1 }- 0x07 431 * \___/ | | | 432 * | | | +--- Transmit TC interrupt enable 433 * | | +----- Receive TC interrupt enable 434 * | +------- 1.8432 MHz 435 * +----------- Reserved 436 */ 437#define CONFIG_SYS_SC520_UART1CTL 0x07 438#define CONFIG_SYS_SC520_UART2CTL 0x07 439 440/*----------------------------------------------------------------------- 441 * System Arbiter Control 442 * 443 * 00000 1 1 0 }- 0x06 444 * \___/ | | | 445 * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt 446 * | | +----- The system arbiter operates in concurrent mode 447 * | +------- Park the PCI bus on the last master that acquired the bus 448 * +----------- Reserved 449 */ 450#define CONFIG_SYS_SC520_SYSARBCTL 0x06 451 452/*----------------------------------------------------------------------- 453 * System Arbiter Master Enable 454 * 455 * 00000000000 0 0 0 1 1 }- 0x06 456 * \_________/ | | | | | 457 * | | | | | +--- PCI master REQ0 enabled (Ethernet 1) 458 * | | | | +----- PCI master REQ1 enabled (Ethernet 2) 459 * | | | +------- PCI master REQ2 disabled 460 * | | +--------- PCI master REQ3 disabled 461 * | +----------- PCI master REQ4 disabled 462 * +------------------ Reserved 463 */ 464#define CONFIG_SYS_SC520_SYSARBMENB 0x0003 465 466/*----------------------------------------------------------------------- 467 * System Arbiter Master Enable 468 * 469 * 0 0000 0 00 0000 1 000 }- 0x06 470 * | \__/ | \| \__/ | \_/ 471 * | | | | | | +---- Reserved 472 * | | | | | +------- Enable CPU-to-PCI bus write posting 473 * | | | | +---------- Reserved 474 * | | | +-------------- PCI bus reads to SDRAM are not automatically 475 * | | | retried 476 * | | +----------------- Target read FIFOs are not snooped during write 477 * | | transactions 478 * | +-------------------- Reserved 479 * +------------------------ Deassert the PCI bus reset signal 480 */ 481#define CONFIG_SYS_SC520_HBCTL 0x08 482 483/*----------------------------------------------------------------------- 484 * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS 485 * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800 486 * \ / | | | | \----+----/ \-----+------/ 487 * | | | | | | +---------- Start at 0x38000000 488 * | | | | | +----------------------- 512kB Region Size 489 * | | | | | ((7 + 1) * 64kB) 490 * | | | | +------------------------------ 64kB Page Size 491 * | | | +-------------------------------- Writes Enabled (So it can be 492 * | | | reprogrammed!) 493 * | | +---------------------------------- Caching Disabled 494 * | +------------------------------------ Execution Enabled 495 * +--------------------------------------- BOOTCS 496 */ 497#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800 498 499/*----------------------------------------------------------------------- 500 * Cache-As-RAM (Targets Boot Flash) 501 * 502 * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200 503 * \ / | | | | \--+--/ \-------+--------/ 504 * | | | | | | +------------ Start at 0x19200000 505 * | | | | | +------------------------- 64k Region Size 506 * | | | | | ((15 + 1) * 4kB) 507 * | | | | +------------------------------ 4kB Page Size 508 * | | | +-------------------------------- Writes Enabled 509 * | | +---------------------------------- Caching Enabled 510 * | +------------------------------------ Execution Prevented 511 * +--------------------------------------- BOOTCS 512 */ 513#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200 514 515/*----------------------------------------------------------------------- 516 * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6 517 * 518 * 001 110 0 000100000 0001000000000000 }- 0x38201000 519 * \ / \ / | \---+---/ \------+-------/ 520 * | | | | +----------- Start at 0x00001000 521 * | | | +------------------------ 33 Bytes (0x20 + 1) 522 * | | +------------------------------ Ignored 523 * | +--------------------------------- GPCS6 524 * +------------------------------------- GP Bus I/O 525 */ 526#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000 527 528/*----------------------------------------------------------------------- 529 * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5 530 * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7 531 * 532 * 010 101 0 0000000 100000000000000000 }- 0x54020000 533 * 010 111 0 0000000 100000000000000001 }- 0x5c020001 534 * \ / \ / | \--+--/ \-------+--------/ 535 * | | | | +------------ Start at 0x200000000 536 * | | | | 0x200010000 537 * | | | +------------------------- 4kB Region Size 538 * | | | ((0 + 1) * 4kB) 539 * | | +------------------------------ 4k Page Size 540 * | +--------------------------------- GPCS5 541 * | GPCS7 542 * +------------------------------------- GP Bus Memory 543 */ 544#define CONFIG_SYS_SC520_CF1_PAR 0x54020000 545#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001 546 547/*----------------------------------------------------------------------- 548 * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0 549 * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3 550 * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4 551 * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5 552 * 553 * 001 000 0 000000111 0001001111111000 }- 0x200713f8 554 * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8 555 * 001 011 0 000000111 0001001011111000 }- 0x300711f8 556 * 001 011 0 000000111 0001001011111000 }- 0x340710f8 557 * \ / \ / | \---+---/ \------+-------/ 558 * | | | | +----------- Start at 0x013f8 559 * | | | | 0x012f8 560 * | | | | 0x011f8 561 * | | | | 0x010f8 562 * | | | +------------------------ 33 Bytes (32 + 1) 563 * | | +------------------------------ Ignored 564 * | +--------------------------------- GPCS6 565 * +------------------------------------- GP Bus I/O 566 */ 567#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8 568#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8 569#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8 570#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8 571 572/*----------------------------------------------------------------------- 573 * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1 574 * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2 575 * 576 * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000 577 * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100 578 * \ / | | | | \----+----/ \-----+------/ 579 * | | | | | | +---------- Start at 0x10000000 580 * | | | | | | 0x11000000 581 * | | | | | +----------------------- 16MB Region Size 582 * | | | | | ((255 + 1) * 64kB) 583 * | | | | +------------------------------ 64kB Page Size 584 * | | | +-------------------------------- Writes Enabled 585 * | | +---------------------------------- Caching Disabled 586 * | +------------------------------------ Execution Enabled 587 * +--------------------------------------- ROMCS1 588 * ROMCS2 589 */ 590#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000 591#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100 592 593/*----------------------------------------------------------------------- 594 * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0 595 * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3 596 * 597 * 010 000 1 00000001111 01100100000000 }- 0x4203d900 598 * 010 011 1 00000001111 01100100010000 }- 0x4e03d910 599 * \ / \ / | \----+----/ \-----+------/ 600 * | | | | +---------- Start at 0x19000000 601 * | | | | 0x19100000 602 * | | | +----------------------- 1MB Region Size 603 * | | | ((15 + 1) * 64kB) 604 * | | +------------------------------ 64kB Page Size 605 * | +--------------------------------- GPCS0 606 * | GPCS3 607 * +------------------------------------- GP Bus Memory 608 */ 609#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900 610#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910 611 612/*----------------------------------------------------------------------- 613 * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4 614 * 615 * 010 100 0 00000000 11000000100000000 }- 0x50018100 616 * \ / \ / | \---+--/ \-------+-------/ 617 * | | | | +----------- Start at 0x18100000 618 * | | | +------------------------ 4kB Region Size 619 * | | | ((0 + 1) * 4kB) 620 * | | +------------------------------ 4kB Page Size 621 * | +--------------------------------- GPCS4 622 * +------------------------------------- GP Bus Memory 623 */ 624#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100 625 626#endif /* __CONFIG_H */ 627