1/* 2 * Configuration for AMCC 460SX Ref (redwood) 3 * 4 * (C) Copyright 2008 5 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25#ifndef __CONFIG_H 26#define __CONFIG_H 27 28/*----------------------------------------------------------------------- 29 * High Level Configuration Options 30 *----------------------------------------------------------------------*/ 31#define CONFIG_4xx 1 /* ... PPC4xx family */ 32#define CONFIG_440 1 /* ... PPC460 family */ 33#define CONFIG_460SX 1 /* ... PPC460 family */ 34#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 35 36#define CONFIG_SYS_TEXT_BASE 0xfffb0000 37 38/*----------------------------------------------------------------------- 39 * Include common defines/options for all AMCC boards 40 *----------------------------------------------------------------------*/ 41#define CONFIG_HOSTNAME redwood 42 43#include "amcc-common.h" 44 45#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ 46 47/*----------------------------------------------------------------------- 48 * Base addresses -- Note these are effective addresses where the 49 * actual resources get mapped (not physical addresses) 50 *----------------------------------------------------------------------*/ 51#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ 52#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ 53 54#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ 55 56#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ 57#define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */ 58#define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */ 59#define CONFIG_SYS_PCIE_MEMSIZE 0x01000000 60 61#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 62#define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000 63#define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000 64#define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000 65#define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000 66#define CONFIG_SYS_PCIE2_CFGBASE 0xba000000 67 68/* PCIe mapped UTL registers */ 69#define CONFIG_SYS_PCIE0_REGBASE 0xd0000000 70#define CONFIG_SYS_PCIE1_REGBASE 0xd0010000 71#define CONFIG_SYS_PCIE2_REGBASE 0xd0020000 72 73/* System RAM mapped to PCI space */ 74#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE 75#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE 76#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) 77 78#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */ 79#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ 80 81/* 82 * Serial Port 83 */ 84#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 85 86/*----------------------------------------------------------------------- 87 * Initial RAM & stack pointer (placed in internal SRAM) 88 *----------------------------------------------------------------------*/ 89#define CONFIG_SYS_TEMP_STACK_OCM 1 90#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE 91#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ 92#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 93 94#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 95#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) 96 97/*----------------------------------------------------------------------- 98 * DDR SDRAM 99 *----------------------------------------------------------------------*/ 100#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ 101#define CONFIG_DDR_ECC 1 /* with ECC support */ 102 103#define CONFIG_SYS_SPD_MAX_DIMMS 2 104 105/* SPD i2c spd addresses */ 106#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR} 107#define IIC0_DIMM0_ADDR 0x53 108#define IIC0_DIMM1_ADDR 0x52 109 110/*----------------------------------------------------------------------- 111 * I2C 112 *----------------------------------------------------------------------*/ 113#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ 114 115#define IIC0_BOOTPROM_ADDR 0x50 116#define IIC0_ALT_BOOTPROM_ADDR 0x54 117 118/* Don't probe these addrs */ 119#define CONFIG_SYS_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} 120 121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ 122 123/*----------------------------------------------------------------------- 124 * Environment 125 *----------------------------------------------------------------------*/ 126#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ 127#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ 128#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ 129 130#define CONFIG_PREBOOT "echo;" \ 131 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ 132 "echo" 133 134#undef CONFIG_BOOTARGS 135 136#define CONFIG_EXTRA_ENV_SETTINGS \ 137 CONFIG_AMCC_DEF_ENV \ 138 CONFIG_AMCC_DEF_ENV_POWERPC \ 139 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 140 CONFIG_AMCC_DEF_ENV_NAND_UPD \ 141 "kernel_addr=fc000000\0" \ 142 "fdt_addr=fc1e0000\0" \ 143 "ramdisk_addr=fc200000\0" \ 144 "" 145 146/*----------------------------------------------------------------------------+ 147| Commands in addition to amcc-common.h 148+----------------------------------------------------------------------------*/ 149#define CONFIG_CMD_SDRAM 150 151#define CONFIG_BOOTCOMMAND "run flash_self" 152 153#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 154 155#define CONFIG_IBM_EMAC4_V4 1 156#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ 157#define CONFIG_PHY_RESET_DELAY 1000 158#define CONFIG_M88E1141_PHY 1 /* Enable phy */ 159#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 160 161#define CONFIG_HAS_ETH0 162#define CONFIG_HAS_ETH1 163#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ 164#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */ 165 166#undef CONFIG_WATCHDOG /* watchdog disabled */ 167 168/*----------------------------------------------------------------------- 169 * FLASH related 170 *----------------------------------------------------------------------*/ 171#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 172#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 173#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ 174 175#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ 176#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 177 178#undef CONFIG_SYS_FLASH_CHECKSUM 179#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 181 182#ifdef CONFIG_ENV_IS_IN_FLASH 183#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ 184#define CONFIG_ENV_ADDR 0xfffa0000 185#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */ 186#endif /* CONFIG_ENV_IS_IN_FLASH */ 187 188/*---------------------------------------------------------------------------*/ 189 190#endif /* __CONFIG_H */ 191