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30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34
35
36
37#define CONFIG_E300 1
38#define CONFIG_MPC83xx 1
39#define CONFIG_MPC834x 1
40#define CONFIG_MPC8349 1
41#define CONFIG_SBC8349 1
42
43#define CONFIG_SYS_TEXT_BASE 0xFF800000
44
45
46#undef CONFIG_MPC83XX_PCI2
47
48
49
50
51
52
53
54#ifdef CONFIG_PCI_33M
55#define CONFIG_83XX_CLKIN 33000000
56#else
57#define CONFIG_83XX_CLKIN 66000000
58#endif
59
60#ifndef CONFIG_SYS_CLK_FREQ
61#ifdef CONFIG_PCI_33M
62#define CONFIG_SYS_CLK_FREQ 33000000
63#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
64#else
65#define CONFIG_SYS_CLK_FREQ 66000000
66#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
67#endif
68#endif
69
70#undef CONFIG_BOARD_EARLY_INIT_F
71
72#define CONFIG_SYS_IMMR 0xE0000000
73
74#undef CONFIG_SYS_DRAM_TEST
75#define CONFIG_SYS_MEMTEST_START 0x00000000
76#define CONFIG_SYS_MEMTEST_END 0x00100000
77
78
79
80
81#undef CONFIG_DDR_ECC
82#undef CONFIG_DDR_ECC_CMD
83#define CONFIG_SPD_EEPROM
84#define CONFIG_SYS_83XX_DDR_USES_CS0
85
86
87
88
89
90
91
92
93
94
95
96#undef CONFIG_DDR_32BIT
97
98#define CONFIG_SYS_DDR_BASE 0x00000000
99#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
101#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
102 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
103#define CONFIG_DDR_2T_TIMING
104
105#if defined(CONFIG_SPD_EEPROM)
106
107
108
109#define SPD_EEPROM_ADDRESS 0x52
110
111#else
112
113
114
115
116#define CONFIG_SYS_DDR_SIZE 256
117#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
118 | CSCONFIG_ROW_BIT_13 \
119 | CSCONFIG_COL_BIT_10)
120#define CONFIG_SYS_DDR_TIMING_1 0x36332321
121#define CONFIG_SYS_DDR_TIMING_2 0x00000800
122#define CONFIG_SYS_DDR_CONTROL 0xc2000000
123#define CONFIG_SYS_DDR_INTERVAL 0x04060100
124
125#if defined(CONFIG_DDR_32BIT)
126
127
128#define CONFIG_SYS_DDR_MODE 0x00000023
129#else
130
131
132#define CONFIG_SYS_DDR_MODE 0x00000022
133#endif
134#endif
135
136
137
138
139#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
140#define CONFIG_SYS_LBC_SDRAM_SIZE 64
141
142
143
144
145#define CONFIG_SYS_FLASH_CFI
146#define CONFIG_FLASH_CFI_DRIVER
147#define CONFIG_SYS_FLASH_BASE 0xFF800000
148#define CONFIG_SYS_FLASH_SIZE 8
149
150
151#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
152 | BR_PS_16 \
153 | BR_MS_GPCM \
154 | BR_V)
155
156#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
157 | OR_GPCM_XAM \
158 | OR_GPCM_CSNT \
159 | OR_GPCM_ACS_DIV2 \
160 | OR_GPCM_XACS \
161 | OR_GPCM_SCY_15 \
162 | OR_GPCM_TRLX_SET \
163 | OR_GPCM_EHTR_SET \
164 | OR_GPCM_EAD)
165
166
167
168#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
169#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
170
171#define CONFIG_SYS_MAX_FLASH_BANKS 1
172#define CONFIG_SYS_MAX_FLASH_SECT 64
173
174#undef CONFIG_SYS_FLASH_CHECKSUM
175#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
176#define CONFIG_SYS_FLASH_WRITE_TOUT 500
177
178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
179
180#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
181#define CONFIG_SYS_RAMBOOT
182#else
183#undef CONFIG_SYS_RAMBOOT
184#endif
185
186#define CONFIG_SYS_INIT_RAM_LOCK 1
187
188#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
189
190#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
191
192#define CONFIG_SYS_GBL_DATA_OFFSET \
193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
194#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
195
196#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
197#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
198
199
200
201
202
203
204
205#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
206#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
207#define CONFIG_SYS_LBC_LBCR 0x00000000
208
209#undef CONFIG_SYS_LB_SDRAM
210
211#ifdef CONFIG_SYS_LB_SDRAM
212
213
214
215
216
217
218
219
220
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223
224
225
226
227
228#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
229 | BR_PS_32 \
230 | BR_MS_SDRAM \
231 | BR_V)
232
233#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
234#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
251 | OR_SDRAM_XAM \
252 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
253 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
254 | OR_SDRAM_EAD)
255
256
257
258#define CONFIG_SYS_LBC_LSRT 0x32000000
259
260#define CONFIG_SYS_LBC_MRTPR 0x20000000
261
262#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
263 | LSDMR_BSMA1516 \
264 | LSDMR_RFCR8 \
265 | LSDMR_PRETOACT6 \
266 | LSDMR_ACTTORW3 \
267 | LSDMR_BL8 \
268 | LSDMR_WRC3 \
269 | LSDMR_CL3)
270
271
272
273
274#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
275#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
276#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
277#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
278#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
279#endif
280
281
282
283
284#define CONFIG_CONS_INDEX 1
285#define CONFIG_SYS_NS16550
286#define CONFIG_SYS_NS16550_SERIAL
287#define CONFIG_SYS_NS16550_REG_SIZE 1
288#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
289
290#define CONFIG_SYS_BAUDRATE_TABLE \
291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
292
293#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
294#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
295
296#define CONFIG_CMDLINE_EDITING 1
297#define CONFIG_AUTO_COMPLETE
298
299#define CONFIG_SYS_HUSH_PARSER
300#ifdef CONFIG_SYS_HUSH_PARSER
301#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
302#endif
303
304
305#define CONFIG_OF_LIBFDT 1
306#define CONFIG_OF_BOARD_SETUP 1
307#define CONFIG_OF_STDOUT_VIA_ALIAS 1
308
309
310#define CONFIG_HARD_I2C
311#undef CONFIG_SOFT_I2C
312#define CONFIG_FSL_I2C
313#define CONFIG_SYS_I2C_SPEED 400000
314#define CONFIG_SYS_I2C_SLAVE 0x7F
315#define CONFIG_SYS_I2C_NOPROBES {0x69}
316#define CONFIG_SYS_I2C1_OFFSET 0x3000
317#define CONFIG_SYS_I2C2_OFFSET 0x3100
318#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
319
320
321
322#define CONFIG_SYS_TSEC1_OFFSET 0x24000
323#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
324#define CONFIG_SYS_TSEC2_OFFSET 0x25000
325#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
326
327
328
329
330
331#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
332#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
333#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
334#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
335#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
336#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
337#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
338#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
339#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
340
341#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
342#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
343#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
344#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
345#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
346#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
347#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
348#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
349#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
350
351#if defined(CONFIG_PCI)
352
353#define PCI_64BIT
354#define PCI_ONE_PCI1
355#if defined(PCI_64BIT)
356#undef PCI_ALL_PCI1
357#undef PCI_TWO_PCI1
358#undef PCI_ONE_PCI1
359#endif
360
361#define CONFIG_PCI_PNP
362
363#undef CONFIG_EEPRO100
364#undef CONFIG_TULIP
365
366#if !defined(CONFIG_PCI_PNP)
367 #define PCI_ENET0_IOADDR 0xFIXME
368 #define PCI_ENET0_MEMADDR 0xFIXME
369 #define PCI_IDSEL_NUMBER 0xFIXME
370#endif
371
372#undef CONFIG_PCI_SCAN_SHOW
373#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
374
375#endif
376
377
378
379
380#define CONFIG_TSEC_ENET
381
382#if defined(CONFIG_TSEC_ENET)
383
384#define CONFIG_TSEC1 1
385#define CONFIG_TSEC1_NAME "TSEC0"
386#define CONFIG_TSEC2 1
387#define CONFIG_TSEC2_NAME "TSEC1"
388#define CONFIG_PHY_BCM5421S 1
389#define TSEC1_PHY_ADDR 0x19
390#define TSEC2_PHY_ADDR 0x1a
391#define TSEC1_PHYIDX 0
392#define TSEC2_PHYIDX 0
393#define TSEC1_FLAGS TSEC_GIGABIT
394#define TSEC2_FLAGS TSEC_GIGABIT
395
396
397#define CONFIG_ETHPRIME "TSEC0"
398
399#endif
400
401
402
403
404#ifndef CONFIG_SYS_RAMBOOT
405 #define CONFIG_ENV_IS_IN_FLASH 1
406 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
407 #define CONFIG_ENV_SECT_SIZE 0x20000
408 #define CONFIG_ENV_SIZE 0x2000
409
410
411#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
412#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
413
414#else
415 #define CONFIG_SYS_NO_FLASH 1
416 #define CONFIG_ENV_IS_NOWHERE 1
417 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
418 #define CONFIG_ENV_SIZE 0x2000
419#endif
420
421#define CONFIG_LOADS_ECHO 1
422#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
423
424
425
426
427
428#define CONFIG_BOOTP_BOOTFILESIZE
429#define CONFIG_BOOTP_BOOTPATH
430#define CONFIG_BOOTP_GATEWAY
431#define CONFIG_BOOTP_HOSTNAME
432
433
434
435
436
437#include <config_cmd_default.h>
438
439#define CONFIG_CMD_I2C
440#define CONFIG_CMD_MII
441#define CONFIG_CMD_PING
442
443#if defined(CONFIG_PCI)
444 #define CONFIG_CMD_PCI
445#endif
446
447#if defined(CONFIG_SYS_RAMBOOT)
448 #undef CONFIG_CMD_SAVEENV
449 #undef CONFIG_CMD_LOADS
450#endif
451
452
453#undef CONFIG_WATCHDOG
454
455
456
457
458#define CONFIG_SYS_LONGHELP
459#define CONFIG_SYS_LOAD_ADDR 0x2000000
460#define CONFIG_SYS_PROMPT "=> "
461
462#if defined(CONFIG_CMD_KGDB)
463 #define CONFIG_SYS_CBSIZE 1024
464#else
465 #define CONFIG_SYS_CBSIZE 256
466#endif
467
468
469#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
470#define CONFIG_SYS_MAXARGS 16
471
472#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
473#define CONFIG_SYS_HZ 1000
474
475
476
477
478
479
480
481#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
482
483#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
484
485#if 1
486#define CONFIG_SYS_HRCW_LOW (\
487 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
488 HRCWL_DDR_TO_SCB_CLK_1X1 |\
489 HRCWL_CSB_TO_CLKIN |\
490 HRCWL_VCO_1X2 |\
491 HRCWL_CORE_TO_CSB_2X1)
492#elif 0
493#define CONFIG_SYS_HRCW_LOW (\
494 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
495 HRCWL_DDR_TO_SCB_CLK_1X1 |\
496 HRCWL_CSB_TO_CLKIN |\
497 HRCWL_VCO_1X4 |\
498 HRCWL_CORE_TO_CSB_3X1)
499#elif 0
500#define CONFIG_SYS_HRCW_LOW (\
501 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
502 HRCWL_DDR_TO_SCB_CLK_1X1 |\
503 HRCWL_CSB_TO_CLKIN |\
504 HRCWL_VCO_1X4 |\
505 HRCWL_CORE_TO_CSB_2X1)
506#elif 0
507#define CONFIG_SYS_HRCW_LOW (\
508 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
509 HRCWL_DDR_TO_SCB_CLK_1X1 |\
510 HRCWL_CSB_TO_CLKIN |\
511 HRCWL_VCO_1X4 |\
512 HRCWL_CORE_TO_CSB_1X1)
513#elif 0
514#define CONFIG_SYS_HRCW_LOW (\
515 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
516 HRCWL_DDR_TO_SCB_CLK_1X1 |\
517 HRCWL_CSB_TO_CLKIN |\
518 HRCWL_VCO_1X4 |\
519 HRCWL_CORE_TO_CSB_1X1)
520#endif
521
522#if defined(PCI_64BIT)
523#define CONFIG_SYS_HRCW_HIGH (\
524 HRCWH_PCI_HOST |\
525 HRCWH_64_BIT_PCI |\
526 HRCWH_PCI1_ARBITER_ENABLE |\
527 HRCWH_PCI2_ARBITER_DISABLE |\
528 HRCWH_CORE_ENABLE |\
529 HRCWH_FROM_0X00000100 |\
530 HRCWH_BOOTSEQ_DISABLE |\
531 HRCWH_SW_WATCHDOG_DISABLE |\
532 HRCWH_ROM_LOC_LOCAL_16BIT |\
533 HRCWH_TSEC1M_IN_GMII |\
534 HRCWH_TSEC2M_IN_GMII)
535#else
536#define CONFIG_SYS_HRCW_HIGH (\
537 HRCWH_PCI_HOST |\
538 HRCWH_32_BIT_PCI |\
539 HRCWH_PCI1_ARBITER_ENABLE |\
540 HRCWH_PCI2_ARBITER_ENABLE |\
541 HRCWH_CORE_ENABLE |\
542 HRCWH_FROM_0X00000100 |\
543 HRCWH_BOOTSEQ_DISABLE |\
544 HRCWH_SW_WATCHDOG_DISABLE |\
545 HRCWH_ROM_LOC_LOCAL_16BIT |\
546 HRCWH_TSEC1M_IN_GMII |\
547 HRCWH_TSEC2M_IN_GMII)
548#endif
549
550
551#define CONFIG_SYS_SICRH 0
552#define CONFIG_SYS_SICRL SICRL_LDP_A
553
554#define CONFIG_SYS_HID0_INIT 0x000000000
555#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
556 | HID0_ENABLE_INSTRUCTION_CACHE)
557
558
559
560
561
562
563
564#define CONFIG_SYS_HID2 HID2_HBE
565
566#define CONFIG_HIGH_BATS 1
567
568
569#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
570 | BATL_PP_RW \
571 | BATL_MEMCOHERENCE)
572#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
573 | BATU_BL_256M \
574 | BATU_VS \
575 | BATU_VP)
576
577
578#ifdef CONFIG_PCI
579#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
580 | BATL_PP_RW \
581 | BATL_MEMCOHERENCE)
582#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
583 | BATU_BL_256M \
584 | BATU_VS \
585 | BATU_VP)
586#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
587 | BATL_PP_RW \
588 | BATL_CACHEINHIBIT \
589 | BATL_GUARDEDSTORAGE)
590#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
591 | BATU_BL_256M \
592 | BATU_VS \
593 | BATU_VP)
594#else
595#define CONFIG_SYS_IBAT1L (0)
596#define CONFIG_SYS_IBAT1U (0)
597#define CONFIG_SYS_IBAT2L (0)
598#define CONFIG_SYS_IBAT2U (0)
599#endif
600
601#ifdef CONFIG_MPC83XX_PCI2
602#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
603 | BATL_PP_RW \
604 | BATL_MEMCOHERENCE)
605#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
606 | BATU_BL_256M \
607 | BATU_VS \
608 | BATU_VP)
609#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
610 | BATL_PP_RW \
611 | BATL_CACHEINHIBIT \
612 | BATL_GUARDEDSTORAGE)
613#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
614 | BATU_BL_256M \
615 | BATU_VS \
616 | BATU_VP)
617#else
618#define CONFIG_SYS_IBAT3L (0)
619#define CONFIG_SYS_IBAT3U (0)
620#define CONFIG_SYS_IBAT4L (0)
621#define CONFIG_SYS_IBAT4U (0)
622#endif
623
624
625#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
626 | BATL_PP_RW \
627 | BATL_CACHEINHIBIT \
628 | BATL_GUARDEDSTORAGE)
629#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
630 | BATU_BL_256M \
631 | BATU_VS \
632 | BATU_VP)
633
634
635#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
636 | BATL_PP_RW \
637 | BATL_MEMCOHERENCE \
638 | BATL_GUARDEDSTORAGE)
639#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
640 | BATU_BL_256M \
641 | BATU_VS \
642 | BATU_VP)
643
644#define CONFIG_SYS_IBAT7L (0)
645#define CONFIG_SYS_IBAT7U (0)
646
647#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
648#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
649#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
650#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
651#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
652#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
653#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
654#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
655#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
656#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
657#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
658#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
659#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
660#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
661#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
662#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
663
664#if defined(CONFIG_CMD_KGDB)
665#define CONFIG_KGDB_BAUDRATE 230400
666#define CONFIG_KGDB_SER_INDEX 2
667#endif
668
669
670
671
672#define CONFIG_ENV_OVERWRITE
673
674#if defined(CONFIG_TSEC_ENET)
675#define CONFIG_HAS_ETH0
676#define CONFIG_HAS_ETH1
677#endif
678
679#define CONFIG_HOSTNAME SBC8349
680#define CONFIG_ROOTPATH "/tftpboot/rootfs"
681#define CONFIG_BOOTFILE "uImage"
682
683
684#define CONFIG_LOADADDR 800000
685
686#define CONFIG_BOOTDELAY 6
687#undef CONFIG_BOOTARGS
688
689#define CONFIG_BAUDRATE 115200
690
691#define CONFIG_EXTRA_ENV_SETTINGS \
692 "netdev=eth0\0" \
693 "hostname=sbc8349\0" \
694 "nfsargs=setenv bootargs root=/dev/nfs rw " \
695 "nfsroot=${serverip}:${rootpath}\0" \
696 "ramargs=setenv bootargs root=/dev/ram rw\0" \
697 "addip=setenv bootargs ${bootargs} " \
698 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
699 ":${hostname}:${netdev}:off panic=1\0" \
700 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
701 "flash_nfs=run nfsargs addip addtty;" \
702 "bootm ${kernel_addr}\0" \
703 "flash_self=run ramargs addip addtty;" \
704 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
705 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
706 "bootm\0" \
707 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
708 "update=protect off ff800000 ff83ffff; " \
709 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
710 "upd=run load update\0" \
711 "fdtaddr=780000\0" \
712 "fdtfile=sbc8349.dtb\0" \
713 ""
714
715#define CONFIG_NFSBOOTCOMMAND \
716 "setenv bootargs root=/dev/nfs rw " \
717 "nfsroot=$serverip:$rootpath " \
718 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
719 "$netdev:off " \
720 "console=$consoledev,$baudrate $othbootargs;" \
721 "tftp $loadaddr $bootfile;" \
722 "tftp $fdtaddr $fdtfile;" \
723 "bootm $loadaddr - $fdtaddr"
724
725#define CONFIG_RAMBOOTCOMMAND \
726 "setenv bootargs root=/dev/ram rw " \
727 "console=$consoledev,$baudrate $othbootargs;" \
728 "tftp $ramdiskaddr $ramdiskfile;" \
729 "tftp $loadaddr $bootfile;" \
730 "tftp $fdtaddr $fdtfile;" \
731 "bootm $loadaddr $ramdiskaddr $fdtaddr"
732
733#define CONFIG_BOOTCOMMAND "run flash_self"
734
735#endif
736