1/* 2 * Faraday FTSDC010 Secure Digital Memory Card Host Controller 3 * 4 * Copyright (C) 2011 Andes Technology Corporation 5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#ifndef __FTSDC010_H 23#define __FTSDC010_H 24 25#ifndef __ASSEMBLY__ 26/* sd controller register */ 27struct ftsdc010_mmc { 28 unsigned int cmd; /* 0x00 - command reg */ 29 unsigned int argu; /* 0x04 - argument reg */ 30 unsigned int rsp0; /* 0x08 - response reg0 */ 31 unsigned int rsp1; /* 0x0c - response reg1 */ 32 unsigned int rsp2; /* 0x10 - response reg2 */ 33 unsigned int rsp3; /* 0x14 - response reg3 */ 34 unsigned int rsp_cmd; /* 0x18 - responded cmd reg */ 35 unsigned int dcr; /* 0x1c - data control reg */ 36 unsigned int dtr; /* 0x20 - data timer reg */ 37 unsigned int dlr; /* 0x24 - data length reg */ 38 unsigned int status; /* 0x28 - status reg */ 39 unsigned int clr; /* 0x2c - clear reg */ 40 unsigned int int_mask; /* 0x30 - intrrupt mask reg */ 41 unsigned int pcr; /* 0x34 - power control reg */ 42 unsigned int ccr; /* 0x38 - clock contorl reg */ 43 unsigned int bwr; /* 0x3c - bus width reg */ 44 unsigned int dwr; /* 0x40 - data window reg */ 45#ifndef CONFIG_FTSDC010_SDIO 46 unsigned int feature; /* 0x44 - feature reg */ 47 unsigned int rev; /* 0x48 - revision reg */ 48#else 49 unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */ 50 unsigned int gpo; /* 0x48 - gerenal purpose output */ 51 unsigned int reserved[8]; /* 0x50 - 0x68 reserved */ 52 unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */ 53 unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */ 54 unsigned int sdio_status; /* 0x74 - SDIO status regi */ 55 unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */ 56 unsigned int feature; /* 0x9c - feature reg */ 57 unsigned int rev; /* 0xa0 - revision reg */ 58#endif /* CONFIG_FTSDC010_SDIO */ 59}; 60 61struct mmc_host { 62 struct ftsdc010_mmc *reg; 63 unsigned int version; /* SDHCI spec. version */ 64 unsigned int clock; /* Current clock (MHz) */ 65 unsigned int fifo_len; /* bytes */ 66 unsigned int last_opcode; /* Last OP Code */ 67 unsigned int card_type; /* Card type */ 68}; 69 70/* functions */ 71int ftsdc010_mmc_init(int dev_index); 72 73#endif /* __ASSEMBLY__ */ 74 75/* global defines */ 76#define FTSDC010_CMD_RETRY 0x100000 77#define FTSDC010_PIO_RETRY 100 /* pio retry times */ 78#define FTSDC010_DELAY_UNIT 100 /* 100 us */ 79 80/* define from Linux kernel - include/linux/mmc/card.h */ 81#define MMC_TYPE_SDIO 2 /* SDIO card */ 82 83/* define for mmc layer */ 84#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) 85 86/* this part is strange */ 87#define FTSDC010_SDIO_CTRL1_REG 0x0000006C 88#define FTSDC010_SDIO_CTRL2_REG 0x0000006C 89#define FTSDC010_SDIO_STATUS_REG 0x00000070 90 91/* 0x00 - command register */ 92#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0) 93#define FTSDC010_CMD_NEED_RSP (1 << 6) 94#define FTSDC010_CMD_LONG_RSP (1 << 7) 95#define FTSDC010_CMD_APP_CMD (1 << 8) 96#define FTSDC010_CMD_CMD_EN (1 << 9) 97#define FTSDC010_CMD_SDC_RST (1 << 10) 98#define FTSDC010_CMD_MMC_INT_STOP (1 << 11) 99 100/* 0x18 - responded command register */ 101#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f) 102#define FTSDC010_RSP_CMD_APP (1 << 6) 103 104/* 0x1c - data control register */ 105#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0) 106#define FTSDC010_DCR_DATA_WRITE (1 << 4) 107#define FTSDC010_DCR_DMA_EN (1 << 5) 108#define FTSDC010_DCR_DATA_EN (1 << 6) 109#ifdef CONFIG_FTSDC010_SDIO 110#define FTSDC010_DCR_FIFOTH (1 << 7) 111#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8) 112#define FTSDC010_DCR_FIFO_RST (1 << 10) 113#endif /* CONFIG_FTSDC010_SDIO */ 114 115#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */ 116#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */ 117#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */ 118 119#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */ 120 121/* CPRM related define */ 122#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008 123#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010 124 125/* 0x28 - status register */ 126#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0) 127#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1) 128#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2) 129#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3) 130#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4) 131#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5) 132#define FTSDC010_STATUS_CMD_SEND (1 << 6) 133#define FTSDC010_STATUS_DATA_END (1 << 7) 134#define FTSDC010_STATUS_FIFO_URUN (1 << 8) 135#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) 136#define FTSDC010_STATUS_CARD_CHANGE (1 << 10) 137#define FTSDC010_STATUS_CARD_DETECT (1 << 11) 138#define FTSDC010_STATUS_WRITE_PROT (1 << 12) 139#ifdef CONFIG_FTSDC010_SDIO 140#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */ 141#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */ 142#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */ 143#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */ 144#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) 145#endif /* CONFIG_FTSDC010_SDIO */ 146 147/* 0x2c - clear register */ 148#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0) 149#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1) 150#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2) 151#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3) 152#define FTSDC010_CLR_RSP_CRC_OK (1 << 4) 153#define FTSDC010_CLR_DATA_CRC_OK (1 << 5) 154#define FTSDC010_CLR_CMD_SEND (1 << 6) 155#define FTSDC010_CLR_DATA_END (1 << 7) 156#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */ 157#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */ 158#define FTSDC010_CLR_CARD_CHANGE (1 << 10) 159#ifdef CONFIG_FTSDC010_SDIO 160#define FTSDC010_CLR_SDIO_IRPT (1 << 16) 161#endif /* CONFIG_FTSDC010_SDIO */ 162 163/* 0x30 - interrupt mask register */ 164#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0) 165#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1) 166#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2) 167#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3) 168#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4) 169#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5) 170#define FTSDC010_INT_MASK_CMD_SEND (1 << 6) 171#define FTSDC010_INT_MASK_DATA_END (1 << 7) 172#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8) 173#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9) 174#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10) 175#ifdef CONFIG_FTSDC010_SDIO 176#define FTSDC010_INT_MASK_CP_READY (1 << 13) 177#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14) 178#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15) 179#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16) 180#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) 181#endif /* CONFIG_FTSDC010_SDIO */ 182 183/* ? */ 184#define FTSDC010_CARD_INSERT 0x0 185#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT 186 187/* 0x34 - power control register */ 188#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0) 189#define FTSDC010_PCR_POWER_ON (1 << 4) 190 191/* 0x38 - clock control register */ 192#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0) 193#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */ 194#define FTSDC010_CCR_CLK_DIS (1 << 8) 195 196/* card type */ 197#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE 198#define FTSDC010_CARD_TYPE_MMC 0x0 199 200/* 0x3c - bus width register */ 201#define FTSDC010_BWR_SINGLE_BUS (1 << 0) 202#define FTSDC010_BWR_WIDE_8_BUS (1 << 1) 203#define FTSDC010_BWR_WIDE_4_BUS (1 << 2) 204#define FTSDC010_BWR_WIDE_BUS_SUPPORT(x) (((x) >> 3) & 0x3) 205#define FTSDC010_BWR_CARD_DETECT (1 << 5) 206 207#define FTSDC010_BWR_1_BUS_SUPPORT 0x0 208#define FTSDC010_BWR_4_BUS_SUPPORT 0x1 209#define FTSDC010_BWR_8_BUS_SUPPORT 0x2 210 211/* 0x44 or 0x9c - feature register */ 212#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff) 213#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8) 214 215#define FTSDC010_FIFO_DEPTH_4 0x04 216#define FTSDC010_FIFO_DEPTH_8 0x08 217#define FTSDC010_FIFO_DEPTH_16 0x10 218 219/* 0x48 or 0xa0 - revision register */ 220#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0) 221#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8) 222#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16) 223 224#ifdef CONFIG_FTSDC010_SDIO 225/* 0x44 - general purpose output */ 226#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0) 227 228/* 0x6c - sdio control register 1 */ 229#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0) 230#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12) 231#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13) 232#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14) 233#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15) 234 235/* 0x70 - sdio control register 2 */ 236#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0) 237#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1) 238 239/* 0x74 - sdio status register */ 240#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff) 241#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef) 242 243#endif /* CONFIG_FTSDC010_SDIO */ 244 245#endif /* __FTSDC010_H */ 246