LXR uboot/nand_spl/nand

   1/*
   2 * (C) Copyright 2006-2008
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 */
  20
  21#include <common.h>
  22#include <nand.h>
  23#include <asm/io.h>
  24
  25static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  26
  27#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  28/*
  29 * NAND command for small page NAND devices (512)
  30 */
  31static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  32{
  33        struct nand_chip *this = mtd->priv;
  34        int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  35
  36        while (!this->dev_ready(mtd))
  37                ;
  38
  39        /* Begin command latch cycle */
  40        this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  41        /* Set ALE and clear CLE to start address cycle */
  42        /* Column address */
  43        this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  44        this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  45        this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
  46                       NAND_CTRL_ALE); /* A[24:17] */
  47#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  48        /* One more address cycle for devices > 32MiB */
  49        this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
  50                       NAND_CTRL_ALE); /* A[28:25] */
  51#endif
  52        /* Latch in address */
  53        this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  54
  55        /*
  56         * Wait a while for the data to be ready
  57         */
  58        while (!this->dev_ready(mtd))
  59                ;
  60
  61        return 0;
  62}
  63#else
  64/*
  65 * NAND command for large page NAND devices (2k)
  66 */
  67static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  68{
  69        struct nand_chip *this = mtd->priv;
  70        int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  71        void (*hwctrl)(struct mtd_info *mtd, int cmd,
  72                        unsigned int ctrl) = this->cmd_ctrl;
  73
  74        while (!this->dev_ready(mtd))
  75                ;
  76
  77        /* Emulate NAND_CMD_READOOB */
  78        if (cmd == NAND_CMD_READOOB) {
  79                offs += CONFIG_SYS_NAND_PAGE_SIZE;
  80                cmd = NAND_CMD_READ0;
  81        }
  82
  83        /* Shift the offset from byte addressing to word addressing. */
  84        if (this->options & NAND_BUSWIDTH_16)
  85                offs >>= 1;
  86
  87        /* Begin command latch cycle */
  88        hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  89        /* Set ALE and clear CLE to start address cycle */
  90        /* Column address */
  91        hwctrl(mtd, offs & 0xff,
  92                       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  93        hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  94        /* Row address */
  95        hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  96        hwctrl(mtd, ((page_addr >> 8) & 0xff),
  97                       NAND_CTRL_ALE); /* A[27:20] */
  98#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  99        /* One more address cycle for devices > 128MiB */
 100        hwctrl(mtd, (page_addr >> 16) & 0x0f,
 101                       NAND_CTRL_ALE); /* A[31:28] */
 102#endif
 103        /* Latch in address */
 104        hwctrl(mtd, NAND_CMD_READSTART,
 105                       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 106        hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 107
 108        /*
 109         * Wait a while for the data to be ready
 110         */
 111        while (!this->dev_ready(mtd))
 112                ;
 113
 114        return 0;
 115}
 116#endif
 117
 118static int nand_is_bad_block(struct mtd_info *mtd, int block)
 119{
 120        struct nand_chip *this = mtd->priv;
 121
 122        nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 123
 124        /*
 125         * Read one byte (or two if it's a 16 bit chip).
 126         */
 127        if (this->options & NAND_BUSWIDTH_16) {
 128                if (readw(this->IO_ADDR_R) != 0xffff)
 129                        return 1;
 130        } else {
 131                if (readb(this->IO_ADDR_R) != 0xff)
 132                        return 1;
 133        }
 134
 135        return 0;
 136}
 137
 138#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
 139static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 140{
 141        struct nand_chip *this = mtd->priv;
 142        u_char *ecc_calc;
 143        u_char *ecc_code;
 144        u_char *oob_data;
 145        int i;
 146        int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 147        int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 148        int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 149        uint8_t *p = dst;
 150
 151        /*
 152         * No malloc available for now, just use some temporary locations
 153         * in SDRAM
 154         */
 155        ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 156        ecc_code = ecc_calc + 0x100;
 157        oob_data = ecc_calc + 0x200;
 158
 159        nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
 160        this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 161        nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 162
 163        /* Pick the ECC bytes out of the oob data */
 164        for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 165                ecc_code[i] = oob_data[nand_ecc_pos[i]];
 166
 167
 168        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 169                this->ecc.hwctl(mtd, NAND_ECC_READ);
 170                this->read_buf(mtd, p, eccsize);
 171                this->ecc.calculate(mtd, p, &ecc_calc[i]);
 172                this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 173        }
 174
 175        return 0;
 176}
 177#else
 178static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 179{
 180        struct nand_chip *this = mtd->priv;
 181        u_char *ecc_calc;
 182        u_char *ecc_code;
 183        u_char *oob_data;
 184        int i;
 185        int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 186        int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 187        int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 188        uint8_t *p = dst;
 189
 190        nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 191
 192        /* No malloc available for now, just use some temporary locations
 193         * in SDRAM
 194         */
 195        ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 196        ecc_code = ecc_calc + 0x100;
 197        oob_data = ecc_calc + 0x200;
 198
 199        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 200                this->ecc.hwctl(mtd, NAND_ECC_READ);
 201                this->read_buf(mtd, p, eccsize);
 202                this->ecc.calculate(mtd, p, &ecc_calc[i]);
 203        }
 204        this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 205
 206        /* Pick the ECC bytes out of the oob data */
 207        for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 208                ecc_code[i] = oob_data[nand_ecc_pos[i]];
 209
 210        eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 211        p = dst;
 212
 213        for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 214                /* No chance to do something with the possible error message
 215                 * from correct_data(). We just hope that all possible errors
 216                 * are corrected by this routine.
 217                 */
 218                this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 219        }
 220
 221        return 0;
 222}
 223#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */
 224
 225static int nand_load(struct mtd_info *mtd, unsigned int offs,
 226                     unsigned int uboot_size, uchar *dst)
 227{
 228        unsigned int block, lastblock;
 229        unsigned int page;
 230
 231        /*
 232         * offs has to be aligned to a page address!
 233         */
 234        block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 235        lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 236        page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 237
 238        while (block <= lastblock) {
 239                if (!nand_is_bad_block(mtd, block)) {
 240                        /*
 241                         * Skip bad blocks
 242                         */
 243                        while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 244                                nand_read_page(mtd, block, page, dst);
 245                                dst += CONFIG_SYS_NAND_PAGE_SIZE;
 246                                page++;
 247                        }
 248
 249                        page = 0;
 250                } else {
 251                        lastblock++;
 252                }
 253
 254                block++;
 255        }
 256
 257        return 0;
 258}
 259
 260/*
 261 * The main entry for NAND booting. It's necessary that SDRAM is already
 262 * configured and available since this code loads the main U-Boot image
 263 * from NAND into SDRAM and starts it from there.
 264 */
 265void nand_boot(void)
 266{
 267        struct nand_chip nand_chip;
 268        nand_info_t nand_info;
 269        __attribute__((noreturn)) void (*uboot)(void);
 270
 271        /*
 272         * Init board specific nand support
 273         */
 274        nand_chip.select_chip = NULL;
 275        nand_info.priv = &nand_chip;
 276        nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
 277        nand_chip.dev_ready = NULL;     /* preset to NULL */
 278        nand_chip.options = 0;
 279        board_nand_init(&nand_chip);
 280
 281        if (nand_chip.select_chip)
 282                nand_chip.select_chip(&nand_info, 0);
 283
 284        /*
 285         * Load U-Boot image from NAND into RAM
 286         */
 287        nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 288                  (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 289
 290#ifdef CONFIG_NAND_ENV_DST
 291        nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 292                  (uchar *)CONFIG_NAND_ENV_DST);
 293
 294#ifdef CONFIG_ENV_OFFSET_REDUND
 295        nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 296                  (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 297#endif
 298#endif
 299
 300        if (nand_chip.select_chip)
 301                nand_chip.select_chip(&nand_info, -1);
 302
 303        /*
 304         * Jump to U-Boot image
 305         */
 306        uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 307        (*uboot)();
 308}
 309