LXR uboot/nand_spl/nand_boot_fsl

   1/*
   2 * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
   3 *
   4 * (C) Copyright 2006-2008
   5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   6 *
   7 * Copyright (c) 2008 Freescale Semiconductor, Inc.
   8 * Author: Scott Wood <scottwood@freescale.com>
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#include <common.h>
  27#include <asm/io.h>
  28#include <asm/fsl_lbc.h>
  29#include <linux/mtd/nand.h>
  30
  31#define WINDOW_SIZE 8192
  32
  33static void nand_wait(void)
  34{
  35        fsl_lbc_t *regs = LBC_BASE_ADDR;
  36
  37        for (;;) {
  38                uint32_t status = in_be32(&regs->ltesr);
  39
  40                if (status == 1)
  41                        return;
  42
  43                if (status & 1) {
  44                        puts("read failed (ltesr)\n");
  45                        for (;;);
  46                }
  47        }
  48}
  49
  50static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
  51{
  52        fsl_lbc_t *regs = LBC_BASE_ADDR;
  53        uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  54        const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
  55        const int block_shift = large ? 17 : 14;
  56        const int block_size = 1 << block_shift;
  57        const int page_size = large ? 2048 : 512;
  58        const int bad_marker = large ? page_size + 0 : page_size + 5;
  59        int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
  60        int pos = 0;
  61
  62        if (offs & (block_size - 1)) {
  63                puts("bad offset\n");
  64                for (;;);
  65        }
  66
  67        if (large) {
  68                fmr |= FMR_ECCM;
  69                out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
  70                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
  71                out_be32(&regs->fir,
  72                         (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  73                         (FIR_OP_CA  << FIR_OP1_SHIFT) |
  74                         (FIR_OP_PA  << FIR_OP2_SHIFT) |
  75                         (FIR_OP_CW1 << FIR_OP3_SHIFT) |
  76                         (FIR_OP_RBW << FIR_OP4_SHIFT));
  77        } else {
  78                out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
  79                out_be32(&regs->fir,
  80                         (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  81                         (FIR_OP_CA  << FIR_OP1_SHIFT) |
  82                         (FIR_OP_PA  << FIR_OP2_SHIFT) |
  83                         (FIR_OP_RBW << FIR_OP3_SHIFT));
  84        }
  85
  86        out_be32(&regs->fbcr, 0);
  87        clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
  88
  89        while (pos < uboot_size) {
  90                int i = 0;
  91                out_be32(&regs->fbar, offs >> block_shift);
  92
  93                do {
  94                        int j;
  95                        unsigned int page_offs = (offs & (block_size - 1)) << 1;
  96
  97                        out_be32(&regs->ltesr, ~0);
  98                        out_be32(&regs->lteatr, 0);
  99                        out_be32(&regs->fpar, page_offs);
 100                        out_be32(&regs->fmr, fmr);
 101                        out_be32(&regs->lsor, 0);
 102                        nand_wait();
 103
 104                        page_offs %= WINDOW_SIZE;
 105
 106                        /*
 107                         * If either of the first two pages are marked bad,
 108                         * continue to the next block.
 109                         */
 110                        if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
 111                                puts("skipping\n");
 112                                offs = (offs + block_size) & ~(block_size - 1);
 113                                pos &= ~(block_size - 1);
 114                                break;
 115                        }
 116
 117                        for (j = 0; j < page_size; j++)
 118                                dst[pos + j] = buf[page_offs + j];
 119
 120                        pos += page_size;
 121                        offs += page_size;
 122                } while ((offs & (block_size - 1)) && (pos < uboot_size));
 123        }
 124}
 125
 126/*
 127 * The main entry for NAND booting. It's necessary that SDRAM is already
 128 * configured and available since this code loads the main U-Boot image
 129 * from NAND into SDRAM and starts it from there.
 130 */
 131void nand_boot(void)
 132{
 133        __attribute__((noreturn)) void (*uboot)(void);
 134
 135        /*
 136         * Load U-Boot image from NAND into RAM
 137         */
 138        nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 139                  (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 140
 141        /*
 142         * Jump to U-Boot image
 143         */
 144        puts("transfering control\n");
 145        /*
 146         * Clean d-cache and invalidate i-cache, to
 147         * make sure that no stale data is executed.
 148         */
 149        flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 150        uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 151        uboot();
 152}
 153