LXR uboot/arch/arm/cpu/ixp/start.S

   1/* vi: set ts=8 sw=8 noet: */
   2/*
   3 *  u-boot - Startup Code for XScale IXP
   4 *
   5 * Copyright (C) 2003   Kyle Harris <kharris@nexus-tech.net>
   6 *
   7 * Based on startup code example contained in the
   8 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
   9 * samples.
  10 *
  11 * See file CREDITS for list of people who contributed to this
  12 * project.
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License as
  16 * published by the Free Software Foundation; either version 2 of
  17 * the License, or (at your option) any later version.
  18 *
  19 * This program is distributed in the hope that it will be useful,
  20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22 * GNU General Public License for more details.
  23 *
  24 * You should have received a copy of the GNU General Public License
  25 * along with this program; if not, write to the Free Software
  26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 * MA 02111-1307 USA
  28 */
  29
  30#include <asm-offsets.h>
  31#include <config.h>
  32#include <version.h>
  33#include <asm/arch/ixp425.h>
  34
  35#define MMU_Control_M  0x001    /* Enable MMU */
  36#define MMU_Control_A  0x002    /* Enable address alignment faults */
  37#define MMU_Control_C  0x004    /* Enable cache */
  38#define MMU_Control_W  0x008    /* Enable write-buffer */
  39#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
  40#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
  41#define MMU_Control_L  0x040    /* Compatability: */
  42#define MMU_Control_B  0x080    /* Enable Big-Endian */
  43#define MMU_Control_S  0x100    /* Enable system protection */
  44#define MMU_Control_R  0x200    /* Enable ROM protection */
  45#define MMU_Control_I  0x1000   /* Enable Instruction cache */
  46#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
  47#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  48
  49
  50/*
  51 * Macro definitions
  52 */
  53        /* Delay a bit */
  54        .macro DELAY_FOR cycles, reg0
  55        ldr     \reg0, =\cycles
  56        subs    \reg0, \reg0, #1
  57        subne   pc,  pc, #0xc
  58        .endm
  59
  60        /* wait for coprocessor write complete */
  61        .macro CPWAIT reg
  62        mrc  p15,0,\reg,c2,c0,0
  63        mov  \reg,\reg
  64        sub  pc,pc,#4
  65        .endm
  66
  67.globl _start
  68_start:
  69        ldr     pc, _reset
  70        ldr     pc, _undefined_instruction
  71        ldr     pc, _software_interrupt
  72        ldr     pc, _prefetch_abort
  73        ldr     pc, _data_abort
  74        ldr     pc, _not_used
  75        ldr     pc, _irq
  76        ldr     pc, _fiq
  77
  78_reset:                 .word reset
  79_undefined_instruction: .word undefined_instruction
  80_software_interrupt:    .word software_interrupt
  81_prefetch_abort:        .word prefetch_abort
  82_data_abort:            .word data_abort
  83_not_used:              .word not_used
  84_irq:                   .word irq
  85_fiq:                   .word fiq
  86
  87        .balignl 16,0xdeadbeef
  88
  89
  90/*
  91 * Startup Code (reset vector)
  92 *
  93 * do important init only if we don't start from memory!
  94 * - relocate armboot to ram
  95 * - setup stack
  96 * - jump to second stage
  97 */
  98
  99.globl _TEXT_BASE
 100_TEXT_BASE:
 101        .word   CONFIG_SYS_TEXT_BASE
 102
 103/*
 104 * These are defined in the board-specific linker script.
 105 * Subtracting _start from them lets the linker put their
 106 * relative position in the executable instead of leaving
 107 * them null.
 108 */
 109.globl _bss_start_ofs
 110_bss_start_ofs:
 111        .word __bss_start - _start
 112
 113.globl _bss_end_ofs
 114_bss_end_ofs:
 115        .word __bss_end__ - _start
 116
 117.globl _end_ofs
 118_end_ofs:
 119        .word _end - _start
 120
 121#ifdef CONFIG_USE_IRQ
 122/* IRQ stack memory (calculated at run-time) */
 123.globl IRQ_STACK_START
 124IRQ_STACK_START:
 125        .word   0x0badc0de
 126
 127/* IRQ stack memory (calculated at run-time) */
 128.globl FIQ_STACK_START
 129FIQ_STACK_START:
 130        .word 0x0badc0de
 131#endif
 132
 133/* IRQ stack memory (calculated at run-time) + 8 bytes */
 134.globl IRQ_STACK_START_IN
 135IRQ_STACK_START_IN:
 136        .word   0x0badc0de
 137
 138/*
 139 * the actual reset code
 140 */
 141
 142reset:
 143        /* disable mmu, set big-endian */
 144        mov     r0, #0xf8
 145        mcr     p15, 0, r0, c1, c0, 0
 146        CPWAIT  r0
 147
 148        /* invalidate I & D caches & BTB */
 149        mcr     p15, 0, r0, c7, c7, 0
 150        CPWAIT  r0
 151
 152        /* invalidate I & Data TLB */
 153        mcr     p15, 0, r0, c8, c7, 0
 154        CPWAIT r0
 155
 156        /* drain write and fill buffers */
 157        mcr     p15, 0, r0, c7, c10, 4
 158        CPWAIT  r0
 159
 160        /* disable write buffer coalescing */
 161        mrc     p15, 0, r0, c1, c0, 1
 162        orr     r0, r0, #1
 163        mcr     p15, 0, r0, c1, c0, 1
 164        CPWAIT  r0
 165
 166        /* set EXP CS0 to the optimum timing */
 167        ldr     r1, =CONFIG_SYS_EXP_CS0
 168        ldr     r2, =IXP425_EXP_CS0
 169        str     r1, [r2]
 170
 171        /* make sure flash is visible at 0 */
 172        mov     r1, #CONFIG_SYS_SDR_CONFIG
 173        ldr     r2, =IXP425_SDR_CONFIG
 174        str     r1, [r2]
 175
 176        /* disable refresh cycles */
 177        mov     r1, #0
 178        ldr     r3, =IXP425_SDR_REFRESH
 179        str     r1, [r3]
 180
 181        /* send nop command */
 182        mov     r1, #3
 183        ldr     r4, =IXP425_SDR_IR
 184        str     r1, [r4]
 185        DELAY_FOR 0x4000, r0
 186
 187        /* set SDRAM internal refresh val */
 188        ldr     r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
 189        str     r1, [r3]
 190        DELAY_FOR 0x4000, r0
 191
 192        /* send precharge-all command to close all open banks */
 193        mov     r1, #2
 194        str     r1, [r4]
 195        DELAY_FOR 0x4000, r0
 196
 197        /* provide 8 auto-refresh cycles */
 198        mov     r1, #4
 199        mov     r5, #8
 200111:    str     r1, [r4]
 201        DELAY_FOR 0x100, r0
 202        subs    r5, r5, #1
 203        bne     111b
 204
 205        /* set mode register in sdram */
 206        mov     r1, #CONFIG_SYS_SDR_MODE_CONFIG
 207        str     r1, [r4]
 208        DELAY_FOR 0x4000, r0
 209
 210        /* send normal operation command */
 211        mov     r1, #6
 212        str     r1, [r4]
 213        DELAY_FOR 0x4000, r0
 214
 215        /* invalidate I & D caches & BTB */
 216        mcr     p15, 0, r0, c7, c7, 0
 217        CPWAIT  r0
 218
 219        /* invalidate I & Data TLB */
 220        mcr     p15, 0, r0, c8, c7, 0
 221        CPWAIT r0
 222
 223        /* drain write and fill buffers */
 224        mcr     p15, 0, r0, c7, c10, 4
 225        CPWAIT  r0
 226
 227        /* remove flash mirror at 0x00000000 */
 228        ldr     r2, =IXP425_EXP_CFG0
 229        ldr     r1, [r2]
 230        bic     r1, r1, #0x80000000
 231        str     r1, [r2]
 232
 233        /* invalidate I & Data TLB */
 234        mcr     p15, 0, r0, c8, c7, 0
 235        CPWAIT r0
 236
 237        /* enable I cache */
 238        mrc     p15, 0, r0, c1, c0, 0
 239        orr     r0, r0, #MMU_Control_I
 240        mcr     p15, 0, r0, c1, c0, 0
 241        CPWAIT  r0
 242
 243        mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
 244        bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
 245        orr     r0,r0,#0x13
 246        msr     cpsr,r0
 247
 248/* Set initial stackpointer in SDRAM to call board_init_f */
 249call_board_init_f:
 250        ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 251        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 252        ldr     r0,=0x00000000
 253        bl      board_init_f
 254
 255/*------------------------------------------------------------------------------*/
 256
 257/*
 258 * void relocate_code (addr_sp, gd, addr_moni)
 259 *
 260 * This "function" does not return, instead it continues in RAM
 261 * after relocating the monitor code.
 262 *
 263 */
 264        .globl  relocate_code
 265relocate_code:
 266        mov     r4, r0  /* save addr_sp */
 267        mov     r5, r1  /* save addr of gd */
 268        mov     r6, r2  /* save addr of destination */
 269
 270        /* Set up the stack                                                 */
 271stack_setup:
 272        mov     sp, r4
 273
 274        adr     r0, _start
 275        cmp     r0, r6
 276        beq     clear_bss               /* skip relocation */
 277        mov     r1, r6                  /* r1 <- scratch for copy_loop */
 278        ldr     r3, _bss_start_ofs
 279        add     r2, r0, r3              /* r2 <- source end address         */
 280
 281copy_loop:
 282        ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 283        stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 284        cmp     r0, r2                  /* until source end address [r2]    */
 285        blo     copy_loop
 286
 287#ifndef CONFIG_SPL_BUILD
 288        /*
 289         * fix .rel.dyn relocations
 290         */
 291        ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 292        sub     r9, r6, r0              /* r9 <- relocation offset */
 293        ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 294        add     r10, r10, r0            /* r10 <- sym table in FLASH */
 295        ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 296        add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 297        ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 298        add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 299fixloop:
 300        ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 301        add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 302        ldr     r1, [r2, #4]
 303        and     r7, r1, #0xff
 304        cmp     r7, #23                 /* relative fixup? */
 305        beq     fixrel
 306        cmp     r7, #2                  /* absolute fixup? */
 307        beq     fixabs
 308        /* ignore unknown type of fixup */
 309        b       fixnext
 310fixabs:
 311        /* absolute fix: set location to (offset) symbol value */
 312        mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 313        add     r1, r10, r1             /* r1 <- address of symbol in table */
 314        ldr     r1, [r1, #4]            /* r1 <- symbol value */
 315        add     r1, r1, r9              /* r1 <- relocated sym addr */
 316        b       fixnext
 317fixrel:
 318        /* relative fix: increase location by offset */
 319        ldr     r1, [r0]
 320        add     r1, r1, r9
 321fixnext:
 322        str     r1, [r0]
 323        add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 324        cmp     r2, r3
 325        blo     fixloop
 326#endif
 327
 328clear_bss:
 329#ifndef CONFIG_SPL_BUILD
 330        ldr     r0, _bss_start_ofs
 331        ldr     r1, _bss_end_ofs
 332        mov     r4, r6                  /* reloc addr */
 333        add     r0, r0, r4
 334        add     r1, r1, r4
 335        mov     r2, #0x00000000         /* clear                            */
 336
 337clbss_l:str     r2, [r0]                /* clear loop...                    */
 338        add     r0, r0, #4
 339        cmp     r0, r1
 340        bne     clbss_l
 341
 342        bl coloured_LED_init
 343        bl red_led_on
 344#endif
 345
 346/*
 347 * We are done. Do not return, instead branch to second part of board
 348 * initialization, now running from RAM.
 349 */
 350        ldr     r0, _board_init_r_ofs
 351        adr     r1, _start
 352        add     lr, r0, r1
 353        add     lr, lr, r9
 354        /* setup parameters for board_init_r */
 355        mov     r0, r5          /* gd_t */
 356        mov     r1, r6          /* dest_addr */
 357        /* jump to it ... */
 358        mov     pc, lr
 359
 360_board_init_r_ofs:
 361        .word board_init_r - _start
 362
 363_rel_dyn_start_ofs:
 364        .word __rel_dyn_start - _start
 365_rel_dyn_end_ofs:
 366        .word __rel_dyn_end - _start
 367_dynsym_start_ofs:
 368        .word __dynsym_start - _start
 369
 370/****************************************************************************/
 371/*                                                                          */
 372/* Interrupt handling                                                       */
 373/*                                                                          */
 374/****************************************************************************/
 375
 376/* IRQ stack frame                                                          */
 377
 378#define S_FRAME_SIZE    72
 379
 380#define S_OLD_R0        68
 381#define S_PSR           64
 382#define S_PC            60
 383#define S_LR            56
 384#define S_SP            52
 385
 386#define S_IP            48
 387#define S_FP            44
 388#define S_R10           40
 389#define S_R9            36
 390#define S_R8            32
 391#define S_R7            28
 392#define S_R6            24
 393#define S_R5            20
 394#define S_R4            16
 395#define S_R3            12
 396#define S_R2            8
 397#define S_R1            4
 398#define S_R0            0
 399
 400#define MODE_SVC 0x13
 401
 402        /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
 403
 404        .macro  bad_save_user_regs
 405        sub     sp, sp, #S_FRAME_SIZE
 406        stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
 407        add     r8, sp, #S_PC
 408
 409        ldr     r2, IRQ_STACK_START_IN
 410        ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
 411        add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
 412
 413        add     r5, sp, #S_SP
 414        mov     r1, lr
 415        stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
 416        mov     r0, sp
 417        .endm
 418
 419
 420        /* use irq_save_user_regs / irq_restore_user_regs for                */
 421        /* IRQ/FIQ handling                                                  */
 422
 423        .macro  irq_save_user_regs
 424        sub     sp, sp, #S_FRAME_SIZE
 425        stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
 426        add     r8, sp, #S_PC
 427        stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
 428        str     lr, [r8, #0]                    /* Save calling PC           */
 429        mrs     r6, spsr
 430        str     r6, [r8, #4]                    /* Save CPSR                 */
 431        str     r0, [r8, #8]                    /* Save OLD_R0               */
 432        mov     r0, sp
 433        .endm
 434
 435        .macro  irq_restore_user_regs
 436        ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 437        mov     r0, r0
 438        ldr     lr, [sp, #S_PC]                 @ Get PC
 439        add     sp, sp, #S_FRAME_SIZE
 440        subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 441        .endm
 442
 443        .macro get_bad_stack
 444        ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 445
 446        str     lr, [r13]                       @ save caller lr / spsr
 447        mrs     lr, spsr
 448        str     lr, [r13, #4]
 449
 450        mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 451        msr     spsr_c, r13
 452        mov     lr, pc
 453        movs    pc, lr
 454        .endm
 455
 456        .macro get_irq_stack                    @ setup IRQ stack
 457        ldr     sp, IRQ_STACK_START
 458        .endm
 459
 460        .macro get_fiq_stack                    @ setup FIQ stack
 461        ldr     sp, FIQ_STACK_START
 462        .endm
 463
 464
 465/****************************************************************************/
 466/*                                                                          */
 467/* exception handlers                                                       */
 468/*                                                                          */
 469/****************************************************************************/
 470
 471        .align  5
 472undefined_instruction:
 473        get_bad_stack
 474        bad_save_user_regs
 475        bl      do_undefined_instruction
 476
 477        .align  5
 478software_interrupt:
 479        get_bad_stack
 480        bad_save_user_regs
 481        bl      do_software_interrupt
 482
 483        .align  5
 484prefetch_abort:
 485        get_bad_stack
 486        bad_save_user_regs
 487        bl      do_prefetch_abort
 488
 489        .align  5
 490data_abort:
 491        get_bad_stack
 492        bad_save_user_regs
 493        bl      do_data_abort
 494
 495        .align  5
 496not_used:
 497        get_bad_stack
 498        bad_save_user_regs
 499        bl      do_not_used
 500
 501#ifdef CONFIG_USE_IRQ
 502
 503        .align  5
 504irq:
 505        get_irq_stack
 506        irq_save_user_regs
 507        bl      do_irq
 508        irq_restore_user_regs
 509
 510        .align  5
 511fiq:
 512        get_fiq_stack
 513        irq_save_user_regs              /* someone ought to write a more    */
 514        bl      do_fiq                  /* effiction fiq_save_user_regs     */
 515        irq_restore_user_regs
 516
 517#else
 518
 519        .align  5
 520irq:
 521        get_bad_stack
 522        bad_save_user_regs
 523        bl      do_irq
 524
 525        .align  5
 526fiq:
 527        get_bad_stack
 528        bad_save_user_regs
 529        bl      do_fiq
 530
 531#endif
 532
 533/****************************************************************************/
 534/*                                                                          */
 535/* Reset function: Use Watchdog to reset                                    */
 536/*                                                                          */
 537/****************************************************************************/
 538
 539        .align  5
 540.globl reset_cpu
 541
 542reset_cpu:
 543        ldr     r1, =0x482e
 544        ldr     r2, =IXP425_OSWK
 545        str     r1, [r2]
 546        ldr     r1, =0x0fff
 547        ldr     r2, =IXP425_OSWT
 548        str     r1, [r2]
 549        ldr     r1, =0x5
 550        ldr     r2, =IXP425_OSWE
 551        str     r1, [r2]
 552        b       reset_endless
 553
 554reset_endless:
 555        b       reset_endless
 556