LXR uboot/arch/arm/include/asm/arch-orion5x/cpu.h

   1/*
   2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
   3 *
   4 * Based on original Kirorion5x_ood support which is
   5 * (C) Copyright 2009
   6 * Marvell Semiconductor <www.marvell.com>
   7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   8 *
   9 * See file CREDITS for list of people who contributed to this
  10 * project.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  25 * MA 02110-1301 USA
  26 */
  27
  28#ifndef _ORION5X_CPU_H
  29#define _ORION5X_CPU_H
  30
  31#include <asm/system.h>
  32
  33#ifndef __ASSEMBLY__
  34
  35#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
  36                        | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
  37
  38#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
  39                ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
  40
  41enum memory_bank {
  42        BANK0,
  43        BANK1,
  44        BANK2,
  45        BANK3
  46};
  47
  48enum orion5x_cpu_winen {
  49        ORION5X_WIN_DISABLE,
  50        ORION5X_WIN_ENABLE
  51};
  52
  53enum orion5x_cpu_target {
  54        ORION5X_TARGET_DRAM = 0,
  55        ORION5X_TARGET_DEVICE = 1,
  56        ORION5X_TARGET_PCI = 3,
  57        ORION5X_TARGET_PCIE = 4,
  58        ORION5X_TARGET_SASRAM = 9
  59};
  60
  61enum orion5x_cpu_attrib {
  62        ORION5X_ATTR_DRAM_CS0 = 0x0e,
  63        ORION5X_ATTR_DRAM_CS1 = 0x0d,
  64        ORION5X_ATTR_DRAM_CS2 = 0x0b,
  65        ORION5X_ATTR_DRAM_CS3 = 0x07,
  66        ORION5X_ATTR_PCI_MEM = 0x59,
  67        ORION5X_ATTR_PCI_IO = 0x51,
  68        ORION5X_ATTR_PCIE_MEM = 0x59,
  69        ORION5X_ATTR_PCIE_IO = 0x51,
  70        ORION5X_ATTR_SASRAM = 0x00,
  71        ORION5X_ATTR_DEV_CS0 = 0x1e,
  72        ORION5X_ATTR_DEV_CS1 = 0x1d,
  73        ORION5X_ATTR_DEV_CS2 = 0x1b,
  74        ORION5X_ATTR_BOOTROM = 0x0f
  75};
  76
  77/*
  78 * Device Address MAP BAR values
  79 *
  80 * All addresses and sizes not defined by board code
  81 * will be given default values here.
  82 */
  83
  84#if !defined (ORION5X_ADR_PCIE_MEM)
  85#define ORION5X_ADR_PCIE_MEM    0x90000000
  86#endif
  87
  88#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
  89#define ORION5X_ADR_PCIE_MEM_REMAP_LO   0x90000000
  90#endif
  91
  92#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
  93#define ORION5X_ADR_PCIE_MEM_REMAP_HI   0
  94#endif
  95
  96#if !defined (ORION5X_SZ_PCIE_MEM)
  97#define ORION5X_SZ_PCIE_MEM     (128*1024*1024)
  98#endif
  99
 100#if !defined (ORION5X_ADR_PCIE_IO)
 101#define ORION5X_ADR_PCIE_IO     0xf0000000
 102#endif
 103
 104#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
 105#define ORION5X_ADR_PCIE_IO_REMAP_LO    0x90000000
 106#endif
 107
 108#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
 109#define ORION5X_ADR_PCIE_IO_REMAP_HI    0
 110#endif
 111
 112#if !defined (ORION5X_SZ_PCIE_IO)
 113#define ORION5X_SZ_PCIE_IO      (64*1024)
 114#endif
 115
 116#if !defined (ORION5X_ADR_PCI_MEM)
 117#define ORION5X_ADR_PCI_MEM     0x98000000
 118#endif
 119
 120#if !defined (ORION5X_SZ_PCI_MEM)
 121#define ORION5X_SZ_PCI_MEM      (128*1024*1024)
 122#endif
 123
 124#if !defined (ORION5X_ADR_PCI_IO)
 125#define ORION5X_ADR_PCI_IO      0xf0100000
 126#endif
 127
 128#if !defined (ORION5X_SZ_PCI_IO)
 129#define ORION5X_SZ_PCI_IO       (64*1024)
 130#endif
 131
 132#if !defined (ORION5X_ADR_DEV_CS0)
 133#define ORION5X_ADR_DEV_CS0     0xfa000000
 134#endif
 135
 136#if !defined (ORION5X_SZ_DEV_CS0)
 137#define ORION5X_SZ_DEV_CS0      (2*1024*1024)
 138#endif
 139
 140#if !defined (ORION5X_ADR_DEV_CS1)
 141#define ORION5X_ADR_DEV_CS1     0xf8000000
 142#endif
 143
 144#if !defined (ORION5X_SZ_DEV_CS1)
 145#define ORION5X_SZ_DEV_CS1      (32*1024*1024)
 146#endif
 147
 148#if !defined (ORION5X_ADR_DEV_CS2)
 149#define ORION5X_ADR_DEV_CS2     0xfa800000
 150#endif
 151
 152#if !defined (ORION5X_SZ_DEV_CS2)
 153#define ORION5X_SZ_DEV_CS2      (1*1024*1024)
 154#endif
 155
 156#if !defined (ORION5X_ADR_BOOTROM)
 157#define ORION5X_ADR_BOOTROM     0xFFF80000
 158#endif
 159
 160#if !defined (ORION5X_SZ_BOOTROM)
 161#define ORION5X_SZ_BOOTROM      (512*1024)
 162#endif
 163
 164/*
 165 * PCIE registers are used for SoC device ID and revision
 166 */
 167#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
 168#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
 169
 170/*
 171 * The following definitions are intended for identifying
 172 * the real device and revision on which u-boot is running
 173 * even if it was compiled only for a specific one. Thus,
 174 * these constants must not be considered chip-specific.
 175 */
 176
 177/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
 178#define MV88F5181_DEV_ID        0x5181
 179#define MV88F5181_REV_B1        3
 180#define MV88F5181L_REV_A0       8
 181#define MV88F5181L_REV_A1       9
 182/* Orion-NAS (88F5182) */
 183#define MV88F5182_DEV_ID        0x5182
 184#define MV88F5182_REV_A2        2
 185/* Orion-2 (88F5281) */
 186#define MV88F5281_DEV_ID        0x5281
 187#define MV88F5281_REV_D0        4
 188#define MV88F5281_REV_D1        5
 189#define MV88F5281_REV_D2        6
 190/* Orion-1-90 (88F6183) */
 191#define MV88F6183_DEV_ID        0x6183
 192#define MV88F6183_REV_B0        3
 193
 194/*
 195 * read feroceon core extra feature register
 196 * using co-proc instruction
 197 */
 198static inline unsigned int readfr_extra_feature_reg(void)
 199{
 200        unsigned int val;
 201        asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
 202                        (val) : : "cc");
 203        return val;
 204}
 205
 206/*
 207 * write feroceon core extra feature register
 208 * using co-proc instruction
 209 */
 210static inline void writefr_extra_feature_reg(unsigned int val)
 211{
 212        asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
 213                        (val) : "cc");
 214        isb();
 215}
 216
 217/*
 218 * AHB to Mbus Bridge Registers
 219 * Source: 88F5182 User Manual, Appendix A, section A.4
 220 * Note: only windows 0 and 1 have remap capability.
 221 */
 222struct orion5x_win_registers {
 223        u32 ctrl;
 224        u32 base;
 225        u32 remap_lo;
 226        u32 remap_hi;
 227};
 228
 229/*
 230 * CPU control and status Registers
 231 * Source: 88F5182 User Manual, Appendix A, section A.4
 232 */
 233struct orion5x_cpu_registers {
 234        u32 config;     /*0x20100 */
 235        u32 ctrl_stat;  /*0x20104 */
 236        u32 rstoutn_mask; /* 0x20108 */
 237        u32 sys_soft_rst; /* 0x2010C */
 238        u32 ahb_mbus_cause_irq; /* 0x20110 */
 239        u32 ahb_mbus_mask_irq; /* 0x20114 */
 240};
 241
 242/*
 243 * DDR SDRAM Controller Address Decode Registers
 244 * Source: 88F5182 User Manual, Appendix A, section A.5.1
 245 */
 246struct orion5x_ddr_addr_decode_registers {
 247        u32 base;
 248        u32 size;
 249};
 250
 251/*
 252 * functions
 253 */
 254void reset_cpu(unsigned long ignored);
 255u32 orion5x_device_id(void);
 256u32 orion5x_device_rev(void);
 257unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
 258void timer_init_r(void);
 259#endif /* __ASSEMBLY__ */
 260#endif /* _ORION5X_CPU_H */
 261