1/* 2 * PLL Masks 3 */ 4 5#ifndef __BFIN_PERIPHERAL_PLL__ 6#define __BFIN_PERIPHERAL_PLL__ 7 8/* PLL_CTL Masks */ 9#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 10#define PLL_OFF 0x0002 /* PLL Not Powered */ 11#define STOPCK 0x0008 /* Core Clock Off */ 12#define PDWN 0x0020 /* Enter Deep Sleep Mode */ 13#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ 14#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ 15#define BYPASS 0x0100 /* Bypass the PLL */ 16#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ 17#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ 18 19/* PLL_DIV Masks */ 20#define SSEL 0x000F /* System Select */ 21#define CSEL 0x0030 /* Core Select */ 22#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ 23#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ 24#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ 25#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ 26 27#define CCLK_DIV1 CSEL_DIV1 28#define CCLK_DIV2 CSEL_DIV2 29#define CCLK_DIV4 CSEL_DIV4 30#define CCLK_DIV8 CSEL_DIV8 31 32/* PLL_STAT Masks */ 33#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 34#define FULL_ON 0x0002 /* Processor In Full On Mode */ 35#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 36#define DEEP_SLEEP 0x0008 /* Processor In Deep Sleep Mode */ 37#define SLEEP 0x0010 /* Processor In Sleep Mode */ 38#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 39#define CORE_IDLE 0x0040 /* Processor In IDLE Mode */ 40#define VSTAT 0x0080 /* Voltage Regulator Has Reached Programmed Voltage */ 41 42/* VR_CTL Masks */ 43#ifdef __ADSPBF52x__ 44#define FREQ_MASK 0x3000 /* Switching Oscillator Frequency For Regulator */ 45#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 46#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ 47#else 48#define FREQ_MASK 0x0003 /* Switching Oscillator Frequency For Regulator */ 49#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 50#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 51#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 52#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 53#endif 54 55#define GAIN_MASK 0x000C /* Voltage Level Gain */ 56#define GAIN_5 0x0000 /* GAIN = 5 */ 57#define GAIN_10 0x0004 /* GAIN = 10 */ 58#define GAIN_20 0x0008 /* GAIN = 20 */ 59#define GAIN_50 0x000C /* GAIN = 50 */ 60 61#ifdef __ADSPBF52x__ 62#define VLEV_MASK 0x00F0 /* Internal Voltage Level */ 63#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 64#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 65#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 66#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 67#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 68#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 69#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 70#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 71#else 72#define VLEV_MASK 0x00F0 /* Internal Voltage Level */ 73#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 74#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 75#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 76#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 77#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 78#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 79#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 80#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 81#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 82#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 83#endif 84 85#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 86#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 87#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 88#define GPWE 0x0400 /* General-purpose Wakeup From Hibernate */ 89#define MXVRWE 0x0400 /* MXVR Wakeup From Hibernate */ 90#define USBWE 0x0800 /* USB Wakeup From Hibernate */ 91#define KPADWE 0x1000 /* Keypad Wakeup From Hibernate */ 92#define ROTWE 0x2000 /* Rotary Counter Wakeup From Hibernate */ 93#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ 94#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */ 95 96#endif 97