LXR uboot/arch/m68k/cpu/mcf52x2/cpu

   1/*
   2 * (C) Copyright 2003
   3 * Josef Baumgartner <josef.baumgartner@telex.de>
   4 *
   5 * MCF5282 additionals
   6 * (C) Copyright 2005
   7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   8 * (c) Copyright 2010
   9 * Arcturus Networks Inc. <www.arcturusnetworks.com>
  10 *
  11 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  13 * Hayden Fraser (Hayden.Fraser@freescale.com)
  14 *
  15 * MCF5275 additions
  16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  17 *
  18 * See file CREDITS for list of people who contributed to this
  19 * project.
  20 *
  21 * This program is free software; you can redistribute it and/or
  22 * modify it under the terms of the GNU General Public License as
  23 * published by the Free Software Foundation; either version 2 of
  24 * the License, or (at your option) any later version.
  25 *
  26 * This program is distributed in the hope that it will be useful,
  27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29 * GNU General Public License for more details.
  30 *
  31 * You should have received a copy of the GNU General Public License
  32 * along with this program; if not, write to the Free Software
  33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  34 * MA 02111-1307 USA
  35 */
  36
  37#include <common.h>
  38#include <watchdog.h>
  39#include <asm/immap.h>
  40
  41#if defined(CONFIG_CMD_NET)
  42#include <config.h>
  43#include <net.h>
  44#include <asm/fec.h>
  45#endif
  46
  47#ifndef CONFIG_M5272
  48/* Only 5272 Flexbus chipselect is different from the rest */
  49void init_fbcs(void)
  50{
  51        volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
  52
  53#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  54     && defined(CONFIG_SYS_CS0_CTRL))
  55        fbcs->csar0 = CONFIG_SYS_CS0_BASE;
  56        fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
  57        fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  58#else
  59#warning "Chip Select 0 are not initialized/used"
  60#endif
  61#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  62     && defined(CONFIG_SYS_CS1_CTRL))
  63        fbcs->csar1 = CONFIG_SYS_CS1_BASE;
  64        fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
  65        fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  66#endif
  67#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  68     && defined(CONFIG_SYS_CS2_CTRL))
  69        fbcs->csar2 = CONFIG_SYS_CS2_BASE;
  70        fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
  71        fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  72#endif
  73#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  74     && defined(CONFIG_SYS_CS3_CTRL))
  75        fbcs->csar3 = CONFIG_SYS_CS3_BASE;
  76        fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
  77        fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  78#endif
  79#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  80     && defined(CONFIG_SYS_CS4_CTRL))
  81        fbcs->csar4 = CONFIG_SYS_CS4_BASE;
  82        fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
  83        fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  84#endif
  85#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  86     && defined(CONFIG_SYS_CS5_CTRL))
  87        fbcs->csar5 = CONFIG_SYS_CS5_BASE;
  88        fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
  89        fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  90#endif
  91#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
  92     && defined(CONFIG_SYS_CS6_CTRL))
  93        fbcs->csar6 = CONFIG_SYS_CS6_BASE;
  94        fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
  95        fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
  96#endif
  97#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
  98     && defined(CONFIG_SYS_CS7_CTRL))
  99        fbcs->csar7 = CONFIG_SYS_CS7_BASE;
 100        fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
 101        fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
 102#endif
 103}
 104#endif
 105
 106#if defined(CONFIG_M5208)
 107void cpu_init_f(void)
 108{
 109        volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 110
 111#ifndef CONFIG_WATCHDOG
 112        volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 113
 114        /* Disable the watchdog if we aren't using it */
 115        wdg->cr = 0;
 116#endif
 117
 118        scm1->mpr = 0x77777777;
 119        scm1->pacra = 0;
 120        scm1->pacrb = 0;
 121        scm1->pacrc = 0;
 122        scm1->pacrd = 0;
 123        scm1->pacre = 0;
 124        scm1->pacrf = 0;
 125
 126        /* FlexBus Chipselect */
 127        init_fbcs();
 128
 129        icache_enable();
 130}
 131
 132/* initialize higher level parts of CPU like timers */
 133int cpu_init_r(void)
 134{
 135        return (0);
 136}
 137
 138void uart_port_conf(int port)
 139{
 140        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 141
 142        /* Setup Ports: */
 143        switch (port) {
 144        case 0:
 145                gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
 146                gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
 147                break;
 148        case 1:
 149                gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
 150                gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
 151                break;
 152        case 2:
 153#ifdef CONFIG_SYS_UART2_PRI_GPIO
 154                gpio->par_timer &=
 155                    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
 156                gpio->par_timer |=
 157                    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 158#endif
 159#ifdef CONFIG_SYS_UART2_ALT1_GPIO
 160                gpio->par_feci2c &=
 161                    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
 162                gpio->par_feci2c |=
 163                    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 164#endif
 165#ifdef CONFIG_SYS_UART2_ALT1_GPIO
 166                gpio->par_feci2c &=
 167                    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
 168                gpio->par_feci2c |=
 169                    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 170#endif
 171                break;
 172        }
 173}
 174
 175#if defined(CONFIG_CMD_NET)
 176int fecpin_setclear(struct eth_device *dev, int setclear)
 177{
 178        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 179
 180        if (setclear) {
 181                gpio->par_fec |=
 182                    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
 183                gpio->par_feci2c |=
 184                    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
 185        } else {
 186                gpio->par_fec &=
 187                    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
 188                gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
 189        }
 190        return 0;
 191}
 192#endif                          /* CONFIG_CMD_NET */
 193#endif                          /* CONFIG_M5208 */
 194
 195#if defined(CONFIG_M5253)
 196/*
 197 * Breath some life into the CPU...
 198 *
 199 * Set up the memory map,
 200 * initialize a bunch of registers,
 201 * initialize the UPM's
 202 */
 203void cpu_init_f(void)
 204{
 205        mbar_writeByte(MCFSIM_MPARK, 0x40);     /* 5249 Internal Core takes priority over DMA */
 206        mbar_writeByte(MCFSIM_SYPCR, 0x00);
 207        mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 208        mbar_writeByte(MCFSIM_SWSR, 0x00);
 209        mbar_writeByte(MCFSIM_SWDICR, 0x00);
 210        mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 211        mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 212        mbar_writeByte(MCFSIM_I2CICR, 0x00);
 213        mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 214        mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 215        mbar_writeByte(MCFSIM_ICR6, 0x00);
 216        mbar_writeByte(MCFSIM_ICR7, 0x00);
 217        mbar_writeByte(MCFSIM_ICR8, 0x00);
 218        mbar_writeByte(MCFSIM_ICR9, 0x00);
 219        mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 220
 221        mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 222        mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 223        mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 224
 225        /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
 226
 227        /* FlexBus Chipselect */
 228        init_fbcs();
 229
 230#ifdef CONFIG_FSL_I2C
 231        CONFIG_SYS_I2C_PINMUX_REG =
 232            CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
 233        CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 234#ifdef CONFIG_SYS_I2C2_OFFSET
 235        CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
 236        CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
 237#endif
 238#endif
 239
 240        /* enable instruction cache now */
 241        icache_enable();
 242}
 243
 244/*initialize higher level parts of CPU like timers */
 245int cpu_init_r(void)
 246{
 247        return (0);
 248}
 249
 250void uart_port_conf(int port)
 251{
 252        volatile u32 *par = (u32 *) MMAP_PAR;
 253
 254        /* Setup Ports: */
 255        switch (port) {
 256        case 1:
 257                *par &= 0xFFE7FFFF;
 258                *par |= 0x00180000;
 259                break;
 260        case 2:
 261                *par &= 0xFFFFFFFC;
 262                *par &= 0x00000003;
 263                break;
 264        }
 265}
 266#endif                          /* #if defined(CONFIG_M5253) */
 267
 268#if defined(CONFIG_M5271)
 269void cpu_init_f(void)
 270{
 271#ifndef CONFIG_WATCHDOG
 272        /* Disable the watchdog if we aren't using it */
 273        mbar_writeShort(MCF_WTM_WCR, 0);
 274#endif
 275
 276        /* FlexBus Chipselect */
 277        init_fbcs();
 278
 279#ifdef CONFIG_SYS_MCF_SYNCR
 280        /* Set clockspeed according to board header file */
 281        mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
 282#else
 283        /* Set clockspeed to 100MHz */
 284        mbar_writeLong(MCF_FMPLL_SYNCR,
 285                        MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
 286#endif
 287        while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
 288}
 289
 290/*
 291 * initialize higher level parts of CPU like timers
 292 */
 293int cpu_init_r(void)
 294{
 295        return (0);
 296}
 297
 298void uart_port_conf(int port)
 299{
 300        u16 temp;
 301
 302        /* Setup Ports: */
 303        switch (port) {
 304        case 0:
 305                temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
 306                temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
 307                mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 308                break;
 309        case 1:
 310                temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
 311                temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
 312                mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 313                break;
 314        case 2:
 315                temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
 316                temp |= (0x3000);
 317                mbar_writeShort(MCF_GPIO_PAR_UART, temp);
 318                break;
 319        }
 320}
 321
 322#if defined(CONFIG_CMD_NET)
 323int fecpin_setclear(struct eth_device *dev, int setclear)
 324{
 325        if (setclear) {
 326                /* Enable Ethernet pins */
 327                mbar_writeByte(MCF_GPIO_PAR_FECI2C,
 328                               (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
 329        } else {
 330        }
 331
 332        return 0;
 333}
 334#endif                          /* CONFIG_CMD_NET */
 335#endif
 336
 337#if defined(CONFIG_M5272)
 338/*
 339 * Breath some life into the CPU...
 340 *
 341 * Set up the memory map,
 342 * initialize a bunch of registers,
 343 * initialize the UPM's
 344 */
 345void cpu_init_f(void)
 346{
 347        /* if we come from RAM we assume the CPU is
 348         * already initialized.
 349         */
 350#ifndef CONFIG_MONITOR_IS_IN_RAM
 351        volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
 352        volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
 353        volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 354
 355        sysctrl->sc_scr = CONFIG_SYS_SCR;
 356        sysctrl->sc_spr = CONFIG_SYS_SPR;
 357
 358        /* Setup Ports: */
 359        gpio->gpio_pacnt = CONFIG_SYS_PACNT;
 360        gpio->gpio_paddr = CONFIG_SYS_PADDR;
 361        gpio->gpio_padat = CONFIG_SYS_PADAT;
 362        gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
 363        gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
 364        gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
 365        gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
 366
 367        /* Memory Controller: */
 368        csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
 369        csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
 370
 371#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
 372        csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
 373        csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
 374#endif
 375
 376#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 377        csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
 378        csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
 379#endif
 380
 381#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 382        csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
 383        csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
 384#endif
 385
 386#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
 387        csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
 388        csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
 389#endif
 390
 391#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
 392        csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
 393        csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
 394#endif
 395
 396#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
 397        csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
 398        csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
 399#endif
 400
 401#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
 402        csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
 403        csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
 404#endif
 405
 406#endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 407
 408        /* enable instruction cache now */
 409        icache_enable();
 410
 411}
 412
 413/*
 414 * initialize higher level parts of CPU like timers
 415 */
 416int cpu_init_r(void)
 417{
 418        return (0);
 419}
 420
 421void uart_port_conf(int port)
 422{
 423        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 424
 425        /* Setup Ports: */
 426        switch (port) {
 427        case 0:
 428                gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
 429                gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
 430                break;
 431        case 1:
 432                gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
 433                gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
 434                break;
 435        }
 436}
 437
 438#if defined(CONFIG_CMD_NET)
 439int fecpin_setclear(struct eth_device *dev, int setclear)
 440{
 441        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 442
 443        if (setclear) {
 444                gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
 445                                    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
 446                                    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
 447                                    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
 448        } else {
 449        }
 450        return 0;
 451}
 452#endif                          /* CONFIG_CMD_NET */
 453#endif                          /* #if defined(CONFIG_M5272) */
 454
 455#if defined(CONFIG_M5275)
 456
 457/*
 458 * Breathe some life into the CPU...
 459 *
 460 * Set up the memory map,
 461 * initialize a bunch of registers,
 462 * initialize the UPM's
 463 */
 464void cpu_init_f(void)
 465{
 466        /*
 467         * if we come from RAM we assume the CPU is
 468         * already initialized.
 469         */
 470
 471#ifndef CONFIG_MONITOR_IS_IN_RAM
 472        volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
 473        volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 474
 475        /* Kill watchdog so we can initialize the PLL */
 476        wdog_reg->wcr = 0;
 477
 478        /* FlexBus Chipselect */
 479        init_fbcs();
 480#endif                          /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
 481
 482#ifdef CONFIG_FSL_I2C
 483        CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
 484        CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 485#endif
 486
 487        /* enable instruction cache now */
 488        icache_enable();
 489}
 490
 491/*
 492 * initialize higher level parts of CPU like timers
 493 */
 494int cpu_init_r(void)
 495{
 496        return (0);
 497}
 498
 499void uart_port_conf(int port)
 500{
 501        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 502
 503        /* Setup Ports: */
 504        switch (port) {
 505        case 0:
 506                gpio->par_uart &= ~UART0_ENABLE_MASK;
 507                gpio->par_uart |= UART0_ENABLE_MASK;
 508                break;
 509        case 1:
 510                gpio->par_uart &= ~UART1_ENABLE_MASK;
 511                gpio->par_uart |= UART1_ENABLE_MASK;
 512                break;
 513        case 2:
 514                gpio->par_uart &= ~UART2_ENABLE_MASK;
 515                gpio->par_uart |= UART2_ENABLE_MASK;
 516                break;
 517        }
 518}
 519
 520#if defined(CONFIG_CMD_NET)
 521int fecpin_setclear(struct eth_device *dev, int setclear)
 522{
 523        struct fec_info_s *info = (struct fec_info_s *) dev->priv;
 524        volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 525
 526        if (setclear) {
 527                /* Enable Ethernet pins */
 528                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 529                        gpio->par_feci2c |= 0x0F00;
 530                        gpio->par_fec0hl |= 0xC0;
 531                } else {
 532                        gpio->par_feci2c |= 0x00A0;
 533                        gpio->par_fec1hl |= 0xC0;
 534                }
 535        } else {
 536                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 537                        gpio->par_feci2c &= ~0x0F00;
 538                        gpio->par_fec0hl &= ~0xC0;
 539                } else {
 540                        gpio->par_feci2c &= ~0x00A0;
 541                        gpio->par_fec1hl &= ~0xC0;
 542                }
 543        }
 544
 545        return 0;
 546}
 547#endif                          /* CONFIG_CMD_NET */
 548#endif                          /* #if defined(CONFIG_M5275) */
 549
 550#if defined(CONFIG_M5282)
 551/*
 552 * Breath some life into the CPU...
 553 *
 554 * Set up the memory map,
 555 * initialize a bunch of registers,
 556 * initialize the UPM's
 557 */
 558void cpu_init_f(void)
 559{
 560#ifndef CONFIG_WATCHDOG
 561        /* disable watchdog if we aren't using it */
 562        MCFWTM_WCR = 0;
 563#endif
 564
 565#ifndef CONFIG_MONITOR_IS_IN_RAM
 566        /* Set speed /PLL */
 567        MCFCLOCK_SYNCR =
 568            MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
 569            MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
 570        while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
 571
 572        MCFGPIO_PBCDPAR = 0xc0;
 573
 574        /* Set up the GPIO ports */
 575#ifdef CONFIG_SYS_PEPAR
 576        MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
 577#endif
 578#ifdef  CONFIG_SYS_PFPAR
 579        MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
 580#endif
 581#ifdef CONFIG_SYS_PJPAR
 582        MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
 583#endif
 584#ifdef CONFIG_SYS_PSDPAR
 585        MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
 586#endif
 587#ifdef CONFIG_SYS_PASPAR
 588        MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
 589#endif
 590#ifdef CONFIG_SYS_PEHLPAR
 591        MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 592#endif
 593#ifdef CONFIG_SYS_PQSPAR
 594        MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
 595#endif
 596#ifdef CONFIG_SYS_PTCPAR
 597        MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 598#endif
 599#if defined(CONFIG_SYS_PORTTC)
 600        MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
 601#endif
 602#if defined(CONFIG_SYS_DDRTC)
 603        MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
 604#endif
 605#ifdef CONFIG_SYS_PTDPAR
 606        MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 607#endif
 608#ifdef CONFIG_SYS_PUAPAR
 609        MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 610#endif
 611
 612#if defined(CONFIG_SYS_DDRD)
 613        MCFGPIO_DDRD = CONFIG_SYS_DDRD;
 614#endif
 615#ifdef CONFIG_SYS_DDRUA
 616        MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 617#endif
 618
 619        /* FlexBus Chipselect */
 620        init_fbcs();
 621
 622#endif                          /* CONFIG_MONITOR_IS_IN_RAM */
 623
 624        /* defer enabling cache until boot (see do_go) */
 625        /* icache_enable(); */
 626}
 627
 628/*
 629 * initialize higher level parts of CPU like timers
 630 */
 631int cpu_init_r(void)
 632{
 633        return (0);
 634}
 635
 636void uart_port_conf(int port)
 637{
 638        /* Setup Ports: */
 639        switch (port) {
 640        case 0:
 641                MCFGPIO_PUAPAR &= 0xFc;
 642                MCFGPIO_PUAPAR |= 0x03;
 643                break;
 644        case 1:
 645                MCFGPIO_PUAPAR &= 0xF3;
 646                MCFGPIO_PUAPAR |= 0x0C;
 647                break;
 648        case 2:
 649                MCFGPIO_PASPAR &= 0xFF0F;
 650                MCFGPIO_PASPAR |= 0x00A0;
 651                break;
 652        }
 653}
 654
 655#if defined(CONFIG_CMD_NET)
 656int fecpin_setclear(struct eth_device *dev, int setclear)
 657{
 658        if (setclear) {
 659                MCFGPIO_PASPAR |= 0x0F00;
 660                MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 661        } else {
 662                MCFGPIO_PASPAR &= 0xF0FF;
 663                MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 664        }
 665        return 0;
 666}
 667#endif                  /* CONFIG_CMD_NET */
 668#endif
 669
 670#if defined(CONFIG_M5249)
 671/*
 672 * Breath some life into the CPU...
 673 *
 674 * Set up the memory map,
 675 * initialize a bunch of registers,
 676 * initialize the UPM's
 677 */
 678void cpu_init_f(void)
 679{
 680        /*
 681         *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
 682         *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
 683         *        which is their primary function.
 684         *        ~Jeremy
 685         */
 686        mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
 687        mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
 688        mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
 689        mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
 690        mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
 691        mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
 692
 693        /*
 694         *  dBug Compliance:
 695         *    You can verify these values by using dBug's 'ird'
 696         *    (Internal Register Display) command
 697         *    ~Jeremy
 698         *
 699         */
 700        mbar_writeByte(MCFSIM_MPARK, 0x30);     /* 5249 Internal Core takes priority over DMA */
 701        mbar_writeByte(MCFSIM_SYPCR, 0x00);
 702        mbar_writeByte(MCFSIM_SWIVR, 0x0f);
 703        mbar_writeByte(MCFSIM_SWSR, 0x00);
 704        mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
 705        mbar_writeByte(MCFSIM_SWDICR, 0x00);
 706        mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
 707        mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
 708        mbar_writeByte(MCFSIM_I2CICR, 0x00);
 709        mbar_writeByte(MCFSIM_UART1ICR, 0x00);
 710        mbar_writeByte(MCFSIM_UART2ICR, 0x00);
 711        mbar_writeByte(MCFSIM_ICR6, 0x00);
 712        mbar_writeByte(MCFSIM_ICR7, 0x00);
 713        mbar_writeByte(MCFSIM_ICR8, 0x00);
 714        mbar_writeByte(MCFSIM_ICR9, 0x00);
 715        mbar_writeByte(MCFSIM_QSPIICR, 0x00);
 716
 717        mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
 718        mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
 719        mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 720        mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
 721
 722        /* Setup interrupt priorities for gpio7 */
 723        /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
 724
 725        /* IDE Config registers */
 726        mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
 727        mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
 728
 729        /* FlexBus Chipselect */
 730        init_fbcs();
 731
 732        /* enable instruction cache now */
 733        icache_enable();
 734}
 735
 736/*
 737 * initialize higher level parts of CPU like timers
 738 */
 739int cpu_init_r(void)
 740{
 741        return (0);
 742}
 743
 744void uart_port_conf(int port)
 745{
 746}
 747#endif                          /* #if defined(CONFIG_M5249) */
 748