1/* 2 * (C) Copyright 2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _PPC440SP_H_ 22#define _PPC440SP_H_ 23 24#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ 25 26/* 27 * Some SoC specific registers (not common for all 440 SoC's) 28 */ 29 30/* Memory mapped register */ 31#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* Internal Peripherals */ 32 33#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) 34#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) 35 36#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) 37 38/* SDR's */ 39#define SDR0_PCI0 0x0300 40#define SDR0_SDSTP2 0x0022 41#define SDR0_SDSTP3 0x0023 42 43#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) 44#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) 45 46#define SDR0_PFC1_EM_1000 (0x80000000 >> 10) 47 48#define SDR0_MFR_FIXD (0x80000000 >> 3) /* Workaround for PCI/DMA */ 49 50#define SDR0_SRST0_DMC 0x00200000 51 52#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ 53#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ 54#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ 55#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ 56#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ 57#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ 58#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ 59#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ 60#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ 61 62#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ 63#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ 64#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ 65#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ 66#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ 67#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ 68 69#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ 70#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ 71#define PRADV_MASK 0x07000000 /* Primary Divisor A */ 72#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ 73#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ 74 75/* Strap 1 Register */ 76#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ 77#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ 78#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ 79#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ 80#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ 81#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ 82#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ 83#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ 84#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ 85#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ 86#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ 87#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ 88#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ 89#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ 90#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ 91#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ 92#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ 93#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ 94 95#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) 96#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) 97 98#endif /* _PPC440SP_H_ */ 99