LXR uboot/arch/powerpc/include/asm/ppc4xx-ebc.h

   1/*
   2 * (C) Copyright 2008
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef _PPC4xx_EBC_H_
  25#define _PPC4xx_EBC_H_
  26
  27/*
  28 * Currently there are two register layout versions for the IBM EBC core
  29 * used on 4xx PPC's. The following grouping lists the first layout.
  30 * Within this group there is a slight variation concerning the bit field
  31 * position of the EMPL and EMPH fields:
  32 */
  33#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
  34    defined(CONFIG_405EP) || \
  35    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  36    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  37#define CONFIG_EBC_PPC4xx_IBM_VER1
  38#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
  39    defined(CONFIG_405EP)
  40#define EBC_CFG_EMPH_POS        8
  41#define EBC_CFG_EMPL_POS        6
  42#else
  43#define EBC_CFG_EMPH_POS        6
  44#define EBC_CFG_EMPL_POS        8
  45#endif
  46#endif
  47
  48/*
  49 * Define the max number of EBC banks (chip selects)
  50 */
  51#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
  52    defined(CONFIG_405EZ) || \
  53    defined(CONFIG_440GP) || defined(CONFIG_440GX)
  54#define EBC_NUM_BANKS   8
  55#endif
  56
  57#if defined(CONFIG_405EP)
  58#define EBC_NUM_BANKS   5
  59#endif
  60
  61#if defined(CONFIG_405EX) || \
  62    defined(CONFIG_460SX)
  63#define EBC_NUM_BANKS   4
  64#endif
  65
  66#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  67    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  68    defined(CONFIG_460EX) || defined(CONFIG_460GT)
  69#define EBC_NUM_BANKS   6
  70#endif
  71
  72#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  73    defined(CONFIG_APM821XX)
  74#define EBC_NUM_BANKS   3
  75#endif
  76
  77/* Bank Configuration Register */
  78#define EBC_BXCR(n)             (n)
  79#define EBC_BXCR_BANK_SIZE(n)   (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
  80
  81#define EBC_BXCR_BAS_MASK       PPC_REG_VAL(11, 0xFFF)
  82#define EBC_BXCR_BAS_ENCODE(n)  (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
  83#define EBC_BXCR_BS_MASK        PPC_REG_VAL(14, 0x7)
  84#define EBC_BXCR_BS_1MB         PPC_REG_VAL(14, 0x0)
  85#define EBC_BXCR_BS_2MB         PPC_REG_VAL(14, 0x1)
  86#define EBC_BXCR_BS_4MB         PPC_REG_VAL(14, 0x2)
  87#define EBC_BXCR_BS_8MB         PPC_REG_VAL(14, 0x3)
  88#define EBC_BXCR_BS_16MB        PPC_REG_VAL(14, 0x4)
  89#define EBC_BXCR_BS_32MB        PPC_REG_VAL(14, 0x5)
  90#define EBC_BXCR_BS_64MB        PPC_REG_VAL(14, 0x6)
  91#define EBC_BXCR_BS_128MB       PPC_REG_VAL(14, 0x7)
  92#define EBC_BXCR_BU_MASK        PPC_REG_VAL(16, 0x3)
  93#define EBC_BXCR_BU_NONE        PPC_REG_VAL(16, 0x0)
  94#define EBC_BXCR_BU_R           PPC_REG_VAL(16, 0x1)
  95#define EBC_BXCR_BU_W           PPC_REG_VAL(16, 0x2)
  96#define EBC_BXCR_BU_RW          PPC_REG_VAL(16, 0x3)
  97#define EBC_BXCR_BW_MASK        PPC_REG_VAL(18, 0x3)
  98#define EBC_BXCR_BW_8BIT        PPC_REG_VAL(18, 0x0)
  99#define EBC_BXCR_BW_16BIT       PPC_REG_VAL(18, 0x1)
 100#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
 101#define EBC_BXCR_BW_32BIT       PPC_REG_VAL(18, 0x2)
 102#else
 103#define EBC_BXCR_BW_32BIT       PPC_REG_VAL(18, 0x3)
 104#endif
 105
 106/* Bank Access Parameter Register */
 107#define EBC_BXAP_BME_ENABLED    PPC_REG_VAL(0, 0x1)
 108#define EBC_BXAP_BME_DISABLED   PPC_REG_VAL(0, 0x0)
 109#define EBC_BXAP_TWT_ENCODE(n)  PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
 110#define EBC_BXAP_FWT_ENCODE(n)  PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
 111#define EBC_BXAP_BWT_ENCODE(n)  PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
 112#define EBC_BXAP_BCE_DISABLE    PPC_REG_VAL(9, 0x0)
 113#define EBC_BXAP_BCE_ENABLE     PPC_REG_VAL(9, 0x1)
 114#define EBC_BXAP_BCT_MASK       PPC_REG_VAL(11, 0x3)
 115#define EBC_BXAP_BCT_2TRANS     PPC_REG_VAL(11, 0x0)
 116#define EBC_BXAP_BCT_4TRANS     PPC_REG_VAL(11, 0x1)
 117#define EBC_BXAP_BCT_8TRANS     PPC_REG_VAL(11, 0x2)
 118#define EBC_BXAP_BCT_16TRANS    PPC_REG_VAL(11, 0x3)
 119#define EBC_BXAP_CSN_ENCODE(n)  PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
 120#define EBC_BXAP_OEN_ENCODE(n)  PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
 121#define EBC_BXAP_WBN_ENCODE(n)  PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
 122#define EBC_BXAP_WBF_ENCODE(n)  PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
 123#define EBC_BXAP_TH_ENCODE(n)   PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
 124#define EBC_BXAP_RE_ENABLED     PPC_REG_VAL(23, 0x1)
 125#define EBC_BXAP_RE_DISABLED    PPC_REG_VAL(23, 0x0)
 126#define EBC_BXAP_SOR_DELAYED    PPC_REG_VAL(24, 0x0)
 127#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
 128#define EBC_BXAP_BEM_WRITEONLY  PPC_REG_VAL(25, 0x0)
 129#define EBC_BXAP_BEM_RW         PPC_REG_VAL(25, 0x1)
 130#define EBC_BXAP_PEN_DISABLED   PPC_REG_VAL(26, 0x0)
 131#define EBC_BXAP_PEN_ENABLED    PPC_REG_VAL(26, 0x1)
 132
 133/* Common fields in EBC0_CFG register */
 134#define EBC_CFG_PTD_MASK        PPC_REG_VAL(1, 0x1)
 135#define EBC_CFG_PTD_ENABLE      PPC_REG_VAL(1, 0x0)
 136#define EBC_CFG_PTD_DISABLE     PPC_REG_VAL(1, 0x1)
 137#define EBC_CFG_RTC_MASK        PPC_REG_VAL(4, 0x7)
 138#define EBC_CFG_RTC_16PERCLK    PPC_REG_VAL(4, 0x0)
 139#define EBC_CFG_RTC_32PERCLK    PPC_REG_VAL(4, 0x1)
 140#define EBC_CFG_RTC_64PERCLK    PPC_REG_VAL(4, 0x2)
 141#define EBC_CFG_RTC_128PERCLK   PPC_REG_VAL(4, 0x3)
 142#define EBC_CFG_RTC_256PERCLK   PPC_REG_VAL(4, 0x4)
 143#define EBC_CFG_RTC_512PERCLK   PPC_REG_VAL(4, 0x5)
 144#define EBC_CFG_RTC_1024PERCLK  PPC_REG_VAL(4, 0x6)
 145#define EBC_CFG_RTC_2048PERCLK  PPC_REG_VAL(4, 0x7)
 146#define EBC_CFG_PME_MASK        PPC_REG_VAL(14, 0x1)
 147#define EBC_CFG_PME_DISABLE     PPC_REG_VAL(14, 0x0)
 148#define EBC_CFG_PME_ENABLE      PPC_REG_VAL(14, 0x1)
 149#define EBC_CFG_PMT_MASK        PPC_REG_VAL(19, 0x1F)
 150#define EBC_CFG_PMT_ENCODE(n)   PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
 151
 152/* Now the two versions of the other bits */
 153#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
 154#define EBC_CFG_EBTC_MASK       PPC_REG_VAL(0, 0x1)
 155#define EBC_CFG_EBTC_HI         PPC_REG_VAL(0, 0x0)
 156#define EBC_CFG_EBTC_DRIVEN     PPC_REG_VAL(0, 0x1)
 157#define EBC_CFG_EMPH_MASK       PPC_REG_VAL(EBC_CFG_EMPH_POS, 0x3)
 158#define EBC_CFG_EMPH_ENCODE(n)  PPC_REG_VAL(EBC_CFG_EMPH_POS, \
 159                                                (static_cast(u32, n)) & 0x3)
 160#define EBC_CFG_EMPL_MASK       PPC_REG_VAL(EBC_CFG_EMPL_POS, 0x3)
 161#define EBC_CFG_EMPL_ENCODE(n)  PPC_REG_VAL(EBC_CFG_EMPH_POS, \
 162                                                (static_cast(u32, n)) & 0x3)
 163#define EBC_CFG_CSTC_MASK       PPC_REG_VAL(9, 0x1)
 164#define EBC_CFG_CSTC_HI         PPC_REG_VAL(9, 0x0)
 165#define EBC_CFG_CSTC_DRIVEN     PPC_REG_VAL(9, 0x1)
 166#define EBC_CFG_BPR_MASK        PPC_REG_VAL(11, 0x3)
 167#define EBC_CFG_BPR_1DW         PPC_REG_VAL(11, 0x0)
 168#define EBC_CFG_BPR_2DW         PPC_REG_VAL(11, 0x1)
 169#define EBC_CFG_BPR_4DW         PPC_REG_VAL(11, 0x2)
 170#define EBC_CFG_EMS_MASK        PPC_REG_VAL(13, 0x3)
 171#define EBC_CFG_EMS_8BIT        PPC_REG_VAL(13, 0x0)
 172#define EBC_CFG_EMS_16BIT       PPC_REG_VAL(13, 0x1)
 173#define EBC_CFG_EMS_32BIT       PPC_REG_VAL(13, 0x2)
 174#else
 175#define EBC_CFG_LE_MASK         PPC_REG_VAL(0, 0x1)
 176#define EBC_CFG_LE_UNLOCK       PPC_REG_VAL(0, 0x0)
 177#define EBC_CFG_LE_LOCK         PPC_REG_VAL(0, 0x1)
 178#define EBC_CFG_ATC_MASK        PPC_REG_VAL(5, 0x1)
 179#define EBC_CFG_ATC_HI          PPC_REG_VAL(5, 0x0)
 180#define EBC_CFG_ATC_PREVIOUS    PPC_REG_VAL(5, 0x1)
 181#define EBC_CFG_DTC_MASK        PPC_REG_VAL(6, 0x1)
 182#define EBC_CFG_DTC_HI          PPC_REG_VAL(6, 0x0)
 183#define EBC_CFG_DTC_PREVIOUS    PPC_REG_VAL(6, 0x1)
 184#define EBC_CFG_CTC_MASK        PPC_REG_VAL(7, 0x1)
 185#define EBC_CFG_CTC_HI          PPC_REG_VAL(7, 0x0)
 186#define EBC_CFG_CTC_PREVIOUS    PPC_REG_VAL(7, 0x1)
 187#define EBC_CFG_OEO_MASK        PPC_REG_VAL(8, 0x1)
 188#define EBC_CFG_OEO_HI          PPC_REG_VAL(8, 0x0)
 189#define EBC_CFG_OEO_PREVIOUS    PPC_REG_VAL(8, 0x1)
 190#define EBC_CFG_EMC_MASK        PPC_REG_VAL(9, 0x1)
 191#define EBC_CFG_EMC_NONDEFAULT  PPC_REG_VAL(9, 0x0)
 192#define EBC_CFG_EMC_DEFAULT     PPC_REG_VAL(9, 0x1)
 193#define EBC_CFG_PR_MASK         PPC_REG_VAL(21, 0x3)
 194#define EBC_CFG_PR_16           PPC_REG_VAL(21, 0x0)
 195#define EBC_CFG_PR_32           PPC_REG_VAL(21, 0x1)
 196#define EBC_CFG_PR_64           PPC_REG_VAL(21, 0x2)
 197#define EBC_CFG_PR_128          PPC_REG_VAL(21, 0x3)
 198#endif
 199
 200#endif /* _PPC4xx_EBC_H_ */
 201